Lines Matching +full:8 +full:- +full:cpu
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
14 * Defines x86 CPU feature bits
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
54 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
55 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM ( 1*32+29) /* "lm" Long Mode (x86-64, 64-bit support) */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* "recovery" CPU in recovery mode */
78 /* Other features, Linux-defined mapping, word 3 */
85 #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
88 #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
92 #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */
98 #define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* Clear CPU buffers using VERW */
101 #define X86_FEATURE_ALWAYS ( 3*32+21) /* Always-present feature */
102 #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* "xtopology" CPU topology enum extensions */
105 #define X86_FEATURE_CPUID ( 3*32+25) /* "cpuid" CPU has CPUID instruction itself */
106 #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* "extd_apicid" Extended APICID (8 bits) */
107 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* "amd_dcm" AMD multi-node processor */
108 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* "aperfmperf" P-State hardware coordination feedback c…
113 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
114 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
116 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* "dtes64" 64-bit Debug Store */
118 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
122 #define X86_FEATURE_TM2 ( 4*32+ 8) /* "tm2" Thermal Monitor 2 */
123 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* "ssse3" Supplemental SSE-3 */
126 #define X86_FEATURE_FMA ( 4*32+12) /* "fma" Fused multiply-add */
132 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
133 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
142 #define X86_FEATURE_F16C ( 4*32+29) /* "f16c" 16-bit FP conversions */
146 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
149 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
150 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
151 #define X86_FEATURE_ACE2 ( 5*32+ 8) /* "ace2" Advanced Cryptography Engine v2 */
163 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* "cr8_legacy" CR8 in 32-bit mode */
165 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* "sse4a" SSE-4A */
167 #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* "3dnowprefetch" 3DNow prefetch instructions */
182 #define X86_FEATURE_PTSC ( 6*32+27) /* "ptsc" Performance time-stamp counter */
187 * Auxiliary flags: Linux defined - For features scattered in various
200 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* "hw_pstate" AMD HW-PState */
205 #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* Fill RSB on VM-Exit */
225 /* Virtualization flags: Linux defined, word 8 */
226 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* "tpr_shadow" Intel TPR Shadow */
227 #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 1) /* "flexpriority" Intel FlexPriority */
228 #define X86_FEATURE_EPT ( 8*32+ 2) /* "ept" Intel Extended Page Table */
229 #define X86_FEATURE_VPID ( 8*32+ 3) /* "vpid" Intel Virtual Processor ID */
231 #define X86_FEATURE_VMMCALL ( 8*32+15) /* "vmmcall" Prefer VMMCALL to VMCALL */
232 #define X86_FEATURE_XENPV ( 8*32+16) /* Xen paravirtual guest */
233 #define X86_FEATURE_EPT_AD ( 8*32+17) /* "ept_ad" Intel Extended Page Table access-dirty bit */
234 #define X86_FEATURE_VMCALL ( 8*32+18) /* Hypervisor supports the VMCALL instruction */
235 #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* VMware prefers VMMCALL hypercall instruction */
236 #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* PV unlock function */
237 #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* PV vcpu_is_preempted function */
238 #define X86_FEATURE_TDX_GUEST ( 8*32+22) /* "tdx_guest" Intel Trust Domain Extensions Guest */
240 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
249 #define X86_FEATURE_BMI2 ( 9*32+ 8) /* "bmi2" 2nd group bit manipulation extensions */
257 #define X86_FEATURE_AVX512F ( 9*32+16) /* "avx512f" AVX-512 Foundation */
258 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* "avx512dq" AVX-512 DQ (Double/Quad granular) Instructio…
262 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* "avx512ifma" AVX-512 Integer Fused Multiply-Add instr…
266 #define X86_FEATURE_AVX512PF ( 9*32+26) /* "avx512pf" AVX-512 Prefetch */
267 #define X86_FEATURE_AVX512ER ( 9*32+27) /* "avx512er" AVX-512 Exponential and Reciprocal */
268 #define X86_FEATURE_AVX512CD ( 9*32+28) /* "avx512cd" AVX-512 Conflict Detection */
270 #define X86_FEATURE_AVX512BW ( 9*32+30) /* "avx512bw" AVX-512 BW (Byte/Word granular) Instructions…
271 #define X86_FEATURE_AVX512VL ( 9*32+31) /* "avx512vl" AVX-512 VL (128/256 Vector Length) Extension…
281 * Extended auxiliary flags: Linux defined - for features scattered in various
293 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
294 #define X86_FEATURE_SGX1 (11*32+ 8) /* Basic SGX */
314 #define X86_FEATURE_ZEN2 (11*32+28) /* CPU based on Zen2 microarchitecture */
315 #define X86_FEATURE_ZEN3 (11*32+29) /* CPU based on Zen3 microarchitecture */
316 #define X86_FEATURE_ZEN4 (11*32+30) /* CPU based on Zen4 microarchitecture */
317 #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */
319 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
326 #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */
327 #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
332 #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
337 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
346 …E_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
363 #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
364 #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* "hwp_notify" HWP Notification */
378 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* "flushbyasid" Flush-by-ASID support */
390 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
398 #define X86_FEATURE_GFNI (16*32+ 8) /* "gfni" Galois Field New Instructions */
400 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* "vpclmulqdq" Carry-Less Multiplication Double Quadwor…
402 …512_BITALG (16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
405 #define X86_FEATURE_LA57 (16*32+16) /* "la57" 5-level page tables */
414 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
419 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
420 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* "avx512_4vnniw" AVX-512 Neural Network Instructions…
421 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* "avx512_4fmaps" AVX-512 Multiply Accumulation Singl…
423 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* "avx512_vp2intersect" AVX-512 Intersect for D…
425 #define X86_FEATURE_MD_CLEAR (18*32+10) /* "md_clear" VERW clears CPU buffers */
445 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
449 #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted Stat…
450 #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Neste…
452 #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
453 #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
457 #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages …
459 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
461 #define X86_FEATURE_WRMSR_XX_BASE_NS (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializi…
464 #define X86_FEATURE_AUTOIBRS (20*32+ 8) /* Automatic IBRS */
469 #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */
470 #define X86_FEATURE_SRSO_USER_KERNEL_NO (20*32+30) /* CPU is not affected by SRSO across user/kerne…
473 * Extended auxiliary flags: Linux defined - for features scattered in various
500 #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* "sysret_ss_attrs" SYSRET doesn't fix up SS attrs */
503 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
506 #define X86_BUG_ESPFIX X86_BUG(9) /* IRET to 16-bit SS corrupts ESP/RSP high bits */
510 #define X86_BUG_MONITOR X86_BUG(12) /* "monitor" IPI required to wake up remote CPU */
511 #define X86_BUG_AMD_E400 X86_BUG(13) /* "amd_e400" CPU is among the affected by Erratum 400 */
512 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* "cpu_meltdown" CPU is affected by meltdown attack and …
513 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* "spectre_v1" CPU is affected by Spectre variant 1 attack…
514 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* "spectre_v2" CPU is affected by Spectre variant 2 attack…
515 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* "spec_store_bypass" CPU is affected by speculative…
516 #define X86_BUG_L1TF X86_BUG(18) /* "l1tf" CPU is affected by L1 Terminal Fault */
517 #define X86_BUG_MDS X86_BUG(19) /* "mds" CPU is affected by Microarchitectural data sampling */
518 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* "msbds_only" CPU is only affected by the MSDBS variant …
519 #define X86_BUG_SWAPGS X86_BUG(21) /* "swapgs" CPU is affected by speculation through SWAPGS */
520 #define X86_BUG_TAA X86_BUG(22) /* "taa" CPU is affected by TSX Async Abort(TAA) */
521 #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* "itlb_multihit" CPU may incur MCE during certain page…
522 #define X86_BUG_SRBDS X86_BUG(24) /* "srbds" CPU may leak RNG bits if not mitigated */
523 #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* "mmio_stale_data" CPU is affected by Processor MMIO…
524 #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* "mmio_unknown" CPU is too old and its MMIO Stale Data …
525 #define X86_BUG_RETBLEED X86_BUG(27) /* "retbleed" CPU is affected by RETBleed */
527 #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address…
528 #define X86_BUG_GDS X86_BUG(30) /* "gds" CPU is affected by Gather Data Sampling */
529 #define X86_BUG_TDX_PW_MCE X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does p…
534 #define X86_BUG_RFDS X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling…
535 #define X86_BUG_BHI X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */