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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
17 typedef long long __m64 __attribute__((__vector_size__(8), __aligned__(8)));
19 typedef long long __v1di __attribute__((__vector_size__(8)));
20 typedef int __v2si __attribute__((__vector_size__(8)));
21 typedef short __v4hi __attribute__((__vector_size__(8)));
22 typedef char __v8qi __attribute__((__vector_size__(8)));
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
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H A Davxintrin.h1 /*===---- avxintrin.h - AVX intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
57 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
61 /// Adds two 256-bit vectors of [4 x double].
68 /// A 256-bit vector of [4 x double] containing one of the source operands.
70 /// A 256-bit vector of [4 x double] containing one of the source operands.
71 /// \returns A 256-bit vector of [4 x double] containing the sums of both
79 /// Adds two 256-bit vectors of [8 x float].
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H A Dtmmintrin.h1 /*===---- tmmintrin.h - SSSE3 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("ssse3,no-evex512"), __min_vector_width__(64)))
25 __target__("mmx,ssse3,no-evex512"), \
28 /// Computes the absolute value of each of the packed 8-bit signed
29 /// integers in the source operand and stores the 8-bit unsigned integer
37 /// A 64-bit vector of [8 x i8].
38 /// \returns A 64-bit integer vector containing the absolute values of the
46 /// Computes the absolute value of each of the packed 8-bit signed
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H A Davxvnniint8intrin.h1 /*===-------- avxvnniint8intrin.h - AVXVNNIINT8 intrinsics -----------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
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H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
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H A Dsmmintrin.h1 /*===---- smmintrin.h - SSE4 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("sse4.1,no-evex512"), __min_vector_width__(128)))
41 /// Rounds up each element of the 128-bit vector of [4 x float] to an
42 /// integer and returns the rounded values in a 128-bit vector of
54 /// A 128-bit vector of [4 x float] values to be rounded up.
55 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
58 /// Rounds up each element of the 128-bit vector of [2 x double] to an
59 /// integer and returns the rounded values in a 128-bit vector of
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries -------
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/lib/libc/arm/string/
H A Dmemcpy.S48 /* Word-align the destination buffer */
64 ands ip, r1, #0x03 /* Is src also word-aligned? */
67 /* Quad-align the destination buffer */
70 stmfd sp!, {r4-r9} /* Free up some registers */
80 ldr r4, [r1], #0x04 /* LD:00-03 */
81 ldr r5, [r1], #0x04 /* LD:04-07 */
83 ldr r6, [r1], #0x04 /* LD:08-0b */
84 ldr r7, [r1], #0x04 /* LD:0c-0f */
85 ldr r8, [r1], #0x04 /* LD:10-13 */
86 ldr r9, [r1], #0x04 /* LD:14-17 */
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
40 if (rtwdev->chi in rtw89_get_data_ht_mcs()
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
74 #define PCRF_AZ_SERR_EN_LBN 8
94 * PC_STAT_REG(16bit):
113 #define PCRF_AZ_MDAT_PERR_LBN 8
125 * PC_REV_ID_REG(8bit):
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/freebsd/sys/dev/qat/include/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
15 ICP_QAT_HW_AE_8 = 8,
41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
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/freebsd/contrib/wpa/src/crypto/
H A Dmilenage.c2 * 3GPP AKA - Milenage algorithm (3GPP TS 35.205, .206, .207, .208)
3 * Copyright (c) 2006-2007 <j@w1.fi>
10 * EAP-AKA to be tested properly with real USIM cards.
26 * milenage_f1 - Milenage f1 and f1* algorithms
27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
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/freebsd/contrib/wpa/src/utils/
H A Dbitfield.c25 bf = os_zalloc(sizeof(*bf) + (max_bits + 7) / 8); in bitfield_alloc()
28 bf->bits = (u8 *) (bf + 1); in bitfield_alloc()
29 bf->max_bits = max_bits; in bitfield_alloc()
40 void bitfield_set(struct bitfield *bf, size_t bit) in bitfield_set() argument
42 if (bit >= bf->max_bits) in bitfield_set()
44 bf->bits[bit / 8] |= BIT(bit % 8); in bitfield_set()
48 void bitfield_clear(struct bitfield *bf, size_t bit) in bitfield_clear() argument
50 if (bit >= bf->max_bits) in bitfield_clear()
52 bf->bits[bit / 8] &= ~BIT(bit % 8); in bitfield_clear()
56 int bitfield_is_set(struct bitfield *bf, size_t bit) in bitfield_is_set() argument
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
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H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dieee80211.h1 /*-
2 * Copyright (c) 2020-2024 The FreeBSD Foundation
49 /* 9.4.2.55 Management MIC element (CMAC-256, GMAC-128, and GMAC-256). */
58 #define IEEE80211_CCMP_HDR_LEN 8 /* 802.11i .. net80211 comment */
60 #define IEEE80211_CCMP_MIC_LEN 8 /* || 16 */
61 #define IEEE80211_CCMP_256_HDR_LEN 8
63 #define IEEE80211_GCMP_HDR_LEN 8
70 #define IEEE80211_INVAL_HW_QUEUE ((uint8_t)-1)
79 #define IEEE80211_MAX_MPDU_LEN_HT_BA 4095 /* 9.3.2.1 Format of Data frames; non-VHT non-DMG STA */
90 /* Wi-Fi Peer-to-Peer (P2P) Technical Specification */
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/freebsd/contrib/file/magic/Magdir/
H A Dispell2 #------------------------------------------------------------------------------
17 >2 leshort 0x00 8-bit, no capitalization, 26 flags
18 >2 leshort 0x01 7-bit, no capitalization, 26 flags
19 >2 leshort 0x02 8-bit, capitalization, 26 flags
20 >2 leshort 0x03 7-bit, capitalization, 26 flags
21 >2 leshort 0x04 8-bit, no capitalization, 52 flags
22 >2 leshort 0x05 7-bit, no capitalization, 52 flags
23 >2 leshort 0x06 8-bit, capitalization, 52 flags
24 >2 leshort 0x07 7-bit, capitalization, 52 flags
25 >2 leshort 0x08 8-bit, no capitalization, 128 flags
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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h1 /*-
29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
42 #define FSPI_MCR0_ARDF_EN BIT(6)
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-900
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h20 * Register manipulation macros that expect bit field defines
27 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
28 #define BIT(_n) (1UL << (_n)) macro
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
101 #define AR40XX_MODULE_EN_MIB BIT(0)
104 #define AR40XX_MIB_BUSY BIT(17)
105 #define AR40XX_MIB_CPU_KEEP BIT(20)
112 #define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
115 #define AR40XX_REG_SW_MAC_ADDR0_BYTE4 BITS(8, 8)
116 #define AR40XX_REG_SW_MAC_ADDR0_BYTE4_S 8
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