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/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
146 0 = 1-2Gbps
147 1 = 2-4Gbps (1st tuple default)
148 2 = 4-8Gbps
149 3 = 8-15Gbps (2nd tuple default)
150 4 = 2.5-4Gbps
151 5 = 4-5Gbps
152 6 = 5-6Gbps
153 7 = 6-16Gbps (3rd tuple default).
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h147 MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
193 * bit 0: G3 (6.0Gbps) with SSC
[all …]
H A Dmv_94xx.c111 * FFE_RES_SEL [6:4] in set_phy_ffe_tuning()
139 * DFE_UPDATE_EN [11:6] in set_phy_ffe_tuning()
147 tmp |= ((0x3F << 6) | (0x0 << 0)); in set_phy_ffe_tuning()
177 /* support 1.5 Gbps */ in set_phy_rate()
185 /* support 1.5, 3.0 Gbps */ in set_phy_rate()
192 /* support 1.5, 3.0, 6.0 Gbps */ in set_phy_rate()
233 /*set default phy_rate = 6Gbps*/ in mvs_94xx_config_reg_from_hba()
408 /* set 6G/3G/1.5G, multiplexing, without SSC */ in mvs_94xx_init()
411 /* set 6G/3G/1.5G, multiplexing, with and without SSC */ in mvs_94xx_init()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h62 #define FEATURE_DPM_XGMI_BIT 6
193 #define THROTTLER_TEMP_VR_SOC_BIT 6
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
436 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h51 #define NUM_OD_FAN_MAX_POINTS 6
82 #define FEATURE_DPM_MP0CLK_BIT 6
201 #define THROTTLER_TEMP_VR_MEM1_BIT 6
225 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h44 #define FEATURE_DPM_XGMI_BIT 6
117 #define THROTTLER_TEMP_GPU_BIT 6
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
553 #define TABLE_I2C_COMMANDS 6
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
73 #define CFG_0_RX_CRC_STRIP_SHIFT 6
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
131 #define CFG_3_CF_TIMEOUT_SHIFT 6
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_rate_tc_bw.py39 - Total bandwidth: 1Gbps
217 {"index": 6, "bw": 0},
280 gbps = bits_per_second / 1e9
281 if gbps < min_expected_gbps:
283 f"iperf3 bandwidth too low: {gbps:.2f} Gbps "
284 f"(expected ≥ {min_expected_gbps} Gbps)"
287 return gbps
372 f"Total bandwidth {total:.2f} Gbps < minimum "
373 f"{validator.total_min_expected:.2f} Gbps; "
379 f"Total bandwidth {total:.2f} Gbps exceeds allowed ceiling "
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
H A Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
/linux/include/rdma/
H A Dopa_port_info.h33 #define OPA_LINKDOWN_REASON_BAD_DLID 6
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
216 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
242 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h116 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
118 #define HCLGE_PHY_MDIX_STATUS_B 6
160 #define HCLGE_VECTOR0_CORERESET_INT_B 6
171 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U
194 #define HCLGE_SUPPORT_100M_BIT BIT(6)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c105 * It is required that PSR and DC5/6 are disabled before any CX0 message
450 return 6; in intel_c10_get_tx_term_ctl()
542 .pll[6] = 0x98,
568 .pll[6] = 0x75,
594 .pll[6] = 0xE3,
620 .pll[6] = 0x29,
646 .pll[6] = 0x98,
672 .pll[6] = 0x75,
698 .pll[6] = 0x29,
724 .pll[6] = 0x33,
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts97 gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>;
108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
135 led-6 {
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
187 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c102 #define GS2_RSVD_6_0_MASK GENMASK(6, 0)
111 #define TXDCLK_2X_SEL BIT(6)
136 #define TX_DET_RX_MODE BIT(6)
300 /* 0 1 2 3 4 5 6 7 */
583 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
681 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then in mvebu_a3700_comphy_ethernet_power_on()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
[all …]
H A Dphy-berlin-sata.c26 #define POWER_DOWN_PHY0 BIT(6)
109 /* set PHY up to 6 Gbps */ in phy_berlin_sata_power_on()
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h116 #define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6)
163 #define H_PORT_CB6 6
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
/linux/drivers/ata/
H A DKconfig49 This option will enlarge the kernel by approx. 6KB. Disable it only
285 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
303 tristate "Freescale 3.0Gbps SATA support"
307 This option enables support for Freescale 3.0Gbps SATA controller.
324 tristate "AMD Seattle 6.0Gbps AHCI SATA host controller support"
437 This option enables support for ICH5/6/7/8 Serial ATA
H A Dahci_xgene.c307 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
308 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
324 * 6. If they do not matched and first time, configure the PHY for the linked
485 * 4. If signature class is PMP goto 6
487 * 6. return
550 * go to step 6.
553 * 6. Handle port interrupts.
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c532 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps in analogix_dp_get_max_rx_bandwidth()
534 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps in analogix_dp_get_max_rx_bandwidth()
1316 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || in analogix_dp_bridge_mode_set()
1339 case 6: in analogix_dp_bridge_mode_set()
1398 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". in analogix_dp_dt_parse_pdata()
/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c678 /* For I225, STATUS will indicate 1G speed in both 1 Gbps in igc_get_speed_and_duplex_copper()
679 * and 2.5 Gbps link modes. An additional bit is used in igc_get_speed_and_duplex_copper()
680 * to differentiate between 1 Gbps and 2.5 Gbps. in igc_get_speed_and_duplex_copper()
814 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 in igc_hash_mc_addr()
H A Digc_defines.h34 #define IGC_WUFC_FLX6 BIT(22) /* Flexible Filter 6 Enable */
214 #define NVM_WORD_SIZE_BASE_SHIFT 6
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
261 #define IGC_ICR_RXO BIT(6) /* Rx overrun */
410 #define IGC_BMC2OSPBSIZE_MASK GENMASK(11, 6)
430 #define IGC_TXPB1SIZE_MASK GENMASK(11, 6)
474 #define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
564 #define IGC_TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
565 #define IGC_TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
566 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-jsl-phy.c59 {2, 4, 6, 0x22}
73 /* only support <1.5Gbps */ in ipu6_isys_csi2_phy_config_by_port()
78 val |= FIELD_PREP(GENMASK(6, 1), 13); in ipu6_isys_csi2_phy_config_by_port()
151 index = 6; in ipu6_isys_csi2_set_port_cfg()
/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_config.h224 * 0xc - 1Gbps/Full duplex;
300 #define ICSSG_FDB_ENTRY_TOUCHED BIT(6)

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