Lines Matching +full:6 +full:gbps
105 * It is required that PSR and DC5/6 are disabled before any CX0 message
450 return 6; in intel_c10_get_tx_term_ctl()
542 .pll[6] = 0x98,
568 .pll[6] = 0x75,
594 .pll[6] = 0xE3,
620 .pll[6] = 0x29,
646 .pll[6] = 0x98,
672 .pll[6] = 0x75,
698 .pll[6] = 0x29,
724 .pll[6] = 0x33,
750 .pll[6] = 0x3D,
890 .clock = 1000000, /* 10 Gbps */
914 .clock = 1350000, /* 13.5 Gbps */
939 .clock = 2000000, /* 20 Gbps */
1116 .clock = 1350000, /* 13.5 Gbps */
1180 .pll[6] = 0,
1206 .pll[6] = 0,
1232 .pll[6] = 0,
1258 .pll[6] = 0,
1284 .pll[6] = 0,
1306 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1316 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1326 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1336 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1346 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1356 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1366 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1376 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1386 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1396 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1406 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1416 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1426 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1436 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1446 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1456 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1466 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1476 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1486 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1496 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1506 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1516 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1526 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1536 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1546 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1556 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1566 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1576 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1586 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1596 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1606 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1616 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1626 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1636 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1646 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1656 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1666 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1676 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1686 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1696 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
2299 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2394 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2400 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2404 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2410 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2529 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2531 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2533 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2535 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2537 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2539 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2541 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2542 return 6; in intel_c20_get_dp_rate()
2543 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2545 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2547 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2549 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2551 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2553 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2567 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2568 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2569 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2571 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2573 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2593 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2594 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2595 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2596 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2597 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2702 /* 5. For DP or 6. For HDMI */ in intel_c20_pll_program()
2705 BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, in intel_c20_pll_program()
2706 BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)), in intel_c20_pll_program()
3052 * 6. Program the enabled and disabled owned PHY lane in __intel_cx0pll_enable()
3210 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_enable()
3325 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_cx0pll_disable()
3383 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()