1e9b4ece7SMD Danish Anwar /* SPDX-License-Identifier: GPL-2.0 */ 2e9b4ece7SMD Danish Anwar /* Texas Instruments ICSSG Ethernet driver 3e9b4ece7SMD Danish Anwar * 4e9b4ece7SMD Danish Anwar * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5e9b4ece7SMD Danish Anwar * 6e9b4ece7SMD Danish Anwar */ 7e9b4ece7SMD Danish Anwar 8e9b4ece7SMD Danish Anwar #ifndef __NET_TI_ICSSG_CONFIG_H 9e9b4ece7SMD Danish Anwar #define __NET_TI_ICSSG_CONFIG_H 10e9b4ece7SMD Danish Anwar 11e9b4ece7SMD Danish Anwar struct icssg_buffer_pool_cfg { 12e9b4ece7SMD Danish Anwar __le32 addr; 13e9b4ece7SMD Danish Anwar __le32 len; 14e9b4ece7SMD Danish Anwar } __packed; 15e9b4ece7SMD Danish Anwar 16e9b4ece7SMD Danish Anwar struct icssg_flow_cfg { 17e9b4ece7SMD Danish Anwar __le16 rx_base_flow; 18e9b4ece7SMD Danish Anwar __le16 mgm_base_flow; 19e9b4ece7SMD Danish Anwar } __packed; 20e9b4ece7SMD Danish Anwar 21e9b4ece7SMD Danish Anwar #define PRUETH_PKT_TYPE_CMD 0x10 22e9b4ece7SMD Danish Anwar #define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ 23e9b4ece7SMD Danish Anwar #define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ 24e9b4ece7SMD Danish Anwar #define PRUETH_MAX_TX_DESC 512 25e9b4ece7SMD Danish Anwar #define PRUETH_MAX_RX_DESC 512 26e9b4ece7SMD Danish Anwar #define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ 27e9b4ece7SMD Danish Anwar #define PRUETH_RX_FLOW_DATA 0 28e9b4ece7SMD Danish Anwar 29e9b4ece7SMD Danish Anwar #define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K 30e9b4ece7SMD Danish Anwar #define PRUETH_EMAC_POOLS_PER_SLICE 24 31e9b4ece7SMD Danish Anwar #define PRUETH_EMAC_BUF_POOL_START 8 32e9b4ece7SMD Danish Anwar #define PRUETH_NUM_BUF_POOLS 8 33e9b4ece7SMD Danish Anwar #define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ 34e9b4ece7SMD Danish Anwar #define MSMC_RAM_SIZE \ 35e9b4ece7SMD Danish Anwar (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ 36e9b4ece7SMD Danish Anwar PRUETH_EMAC_RX_CTX_BUF_SIZE * 2)) 37e9b4ece7SMD Danish Anwar 38abd5576bSMD Danish Anwar #define PRUETH_SW_BUF_POOL_SIZE_HOST SZ_4K 39abd5576bSMD Danish Anwar #define PRUETH_SW_NUM_BUF_POOLS_HOST 8 40abd5576bSMD Danish Anwar #define PRUETH_SW_NUM_BUF_POOLS_PER_PRU 4 41abd5576bSMD Danish Anwar #define MSMC_RAM_SIZE_SWITCH_MODE \ 42abd5576bSMD Danish Anwar (MSMC_RAM_SIZE + \ 43abd5576bSMD Danish Anwar (2 * PRUETH_SW_BUF_POOL_SIZE_HOST * PRUETH_SW_NUM_BUF_POOLS_HOST)) 44abd5576bSMD Danish Anwar 45487f7323SMD Danish Anwar #define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1) 46487f7323SMD Danish Anwar 47e9b4ece7SMD Danish Anwar struct icssg_rxq_ctx { 48e9b4ece7SMD Danish Anwar __le32 start[3]; 49e9b4ece7SMD Danish Anwar __le32 end; 50e9b4ece7SMD Danish Anwar } __packed; 51e9b4ece7SMD Danish Anwar 52e9b4ece7SMD Danish Anwar /* Load time Fiwmware Configuration */ 53e9b4ece7SMD Danish Anwar 54e9b4ece7SMD Danish Anwar #define ICSSG_FW_MGMT_CMD_HEADER 0x81 55e9b4ece7SMD Danish Anwar #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 56e9b4ece7SMD Danish Anwar #define ICSSG_FW_MGMT_CMD_TYPE 0x04 57e9b4ece7SMD Danish Anwar #define ICSSG_FW_MGMT_PKT 0x80000000 58e9b4ece7SMD Danish Anwar 59e9b4ece7SMD Danish Anwar struct icssg_r30_cmd { 60e9b4ece7SMD Danish Anwar u32 cmd[4]; 61e9b4ece7SMD Danish Anwar } __packed; 62e9b4ece7SMD Danish Anwar 63e9b4ece7SMD Danish Anwar enum icssg_port_state_cmd { 64e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_DISABLE = 0, 65e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_BLOCK, 66e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_FORWARD, 67e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, 68e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_ACCEPT_ALL, 69e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_ACCEPT_TAGGED, 70e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, 71e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_TAS_TRIGGER, 72e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_TAS_ENABLE, 73e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_TAS_RESET, 74e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_TAS_DISABLE, 75e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, 76e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, 77e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, 78e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, 79e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, 80e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, 81e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, 82e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, 83*56375086SRavi Gunasekaran ICSSG_EMAC_HSR_RX_OFFLOAD_ENABLE, 84*56375086SRavi Gunasekaran ICSSG_EMAC_HSR_RX_OFFLOAD_DISABLE, 85e9b4ece7SMD Danish Anwar ICSSG_EMAC_PORT_MAX_COMMANDS 86e9b4ece7SMD Danish Anwar }; 87e9b4ece7SMD Danish Anwar 88e9b4ece7SMD Danish Anwar #define EMAC_NONE 0xffff0000 89e9b4ece7SMD Danish Anwar #define EMAC_PRU0_P_DI 0xffff0004 90e9b4ece7SMD Danish Anwar #define EMAC_PRU1_P_DI 0xffff0040 91e9b4ece7SMD Danish Anwar #define EMAC_TX_P_DI 0xffff0100 92e9b4ece7SMD Danish Anwar 93e9b4ece7SMD Danish Anwar #define EMAC_PRU0_P_EN 0xfffb0000 94e9b4ece7SMD Danish Anwar #define EMAC_PRU1_P_EN 0xffbf0000 95e9b4ece7SMD Danish Anwar #define EMAC_TX_P_EN 0xfeff0000 96e9b4ece7SMD Danish Anwar 97e9b4ece7SMD Danish Anwar #define EMAC_P_BLOCK 0xffff0040 98e9b4ece7SMD Danish Anwar #define EMAC_TX_P_BLOCK 0xffff0200 99e9b4ece7SMD Danish Anwar #define EMAC_P_UNBLOCK 0xffbf0000 100e9b4ece7SMD Danish Anwar #define EMAC_TX_P_UNBLOCK 0xfdff0000 101e9b4ece7SMD Danish Anwar #define EMAC_LEAN_EN 0xfff70000 102e9b4ece7SMD Danish Anwar #define EMAC_LEAN_DI 0xffff0008 103e9b4ece7SMD Danish Anwar 104e9b4ece7SMD Danish Anwar #define EMAC_ACCEPT_ALL 0xffff0001 105e9b4ece7SMD Danish Anwar #define EMAC_ACCEPT_TAG 0xfffe0002 106e9b4ece7SMD Danish Anwar #define EMAC_ACCEPT_PRIOR 0xfffc0000 107e9b4ece7SMD Danish Anwar 108e9b4ece7SMD Danish Anwar /* Config area lies in DRAM */ 109e9b4ece7SMD Danish Anwar #define ICSSG_CONFIG_OFFSET 0x0 110e9b4ece7SMD Danish Anwar 111e9b4ece7SMD Danish Anwar /* Config area lies in shared RAM */ 112e9b4ece7SMD Danish Anwar #define ICSSG_CONFIG_OFFSET_SLICE0 0 113e9b4ece7SMD Danish Anwar #define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 114e9b4ece7SMD Danish Anwar 115e9b4ece7SMD Danish Anwar #define ICSSG_NUM_NORMAL_PDS 64 116e9b4ece7SMD Danish Anwar #define ICSSG_NUM_SPECIAL_PDS 16 117e9b4ece7SMD Danish Anwar 118e9b4ece7SMD Danish Anwar #define ICSSG_NORMAL_PD_SIZE 8 119e9b4ece7SMD Danish Anwar #define ICSSG_SPECIAL_PD_SIZE 20 120e9b4ece7SMD Danish Anwar 121e9b4ece7SMD Danish Anwar #define ICSSG_FLAG_MASK 0xff00ffff 122e9b4ece7SMD Danish Anwar 1236d6a5751SDiogo Ivo /* SR1.0-specific bits */ 1246d6a5751SDiogo Ivo #define PRUETH_MAX_RX_FLOWS_SR1 4 /* excluding default flow */ 1256d6a5751SDiogo Ivo #define PRUETH_RX_FLOW_DATA_SR1 3 /* highest priority flow */ 1266d6a5751SDiogo Ivo #define PRUETH_MAX_RX_MGM_DESC_SR1 8 1276d6a5751SDiogo Ivo #define PRUETH_MAX_RX_MGM_FLOWS_SR1 2 /* excluding default flow */ 1286d6a5751SDiogo Ivo #define PRUETH_RX_MGM_FLOW_RESPONSE_SR1 0 1296d6a5751SDiogo Ivo #define PRUETH_RX_MGM_FLOW_TIMESTAMP_SR1 1 1306d6a5751SDiogo Ivo 1316d6a5751SDiogo Ivo #define PRUETH_NUM_BUF_POOLS_SR1 16 1326d6a5751SDiogo Ivo #define PRUETH_EMAC_BUF_POOL_START_SR1 8 1336d6a5751SDiogo Ivo #define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1 128 1346d6a5751SDiogo Ivo #define PRUETH_EMAC_BUF_SIZE_SR1 1536 1356d6a5751SDiogo Ivo #define PRUETH_EMAC_NUM_BUF_SR1 4 1366d6a5751SDiogo Ivo #define PRUETH_EMAC_BUF_POOL_SIZE_SR1 (PRUETH_EMAC_NUM_BUF_SR1 * \ 1376d6a5751SDiogo Ivo PRUETH_EMAC_BUF_SIZE_SR1) 1386d6a5751SDiogo Ivo #define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */ 1396d6a5751SDiogo Ivo 1406d6a5751SDiogo Ivo struct icssg_sr1_config { 1416d6a5751SDiogo Ivo __le32 status; /* Firmware status */ 1426d6a5751SDiogo Ivo __le32 addr_lo; /* MSMC Buffer pool base address low. */ 1436d6a5751SDiogo Ivo __le32 addr_hi; /* MSMC Buffer pool base address high. Must be 0 */ 1446d6a5751SDiogo Ivo __le32 tx_buf_sz[16]; /* Array of buffer pool sizes */ 1456d6a5751SDiogo Ivo __le32 num_tx_threads; /* Number of active egress threads, 1 to 4 */ 1466d6a5751SDiogo Ivo __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */ 1476d6a5751SDiogo Ivo __le32 rx_flow_id; /* RX flow id for first rx ring */ 1486d6a5751SDiogo Ivo __le32 rx_mgr_flow_id; /* RX flow id for the first management ring */ 1496d6a5751SDiogo Ivo __le32 flags; /* TBD */ 1506d6a5751SDiogo Ivo __le32 n_burst; /* for debug */ 1516d6a5751SDiogo Ivo __le32 rtu_status; /* RTU status */ 1526d6a5751SDiogo Ivo __le32 info; /* reserved */ 1536d6a5751SDiogo Ivo __le32 reserve; 1546d6a5751SDiogo Ivo __le32 rand_seed; /* Used for the random number generation at fw */ 1556d6a5751SDiogo Ivo } __packed; 1566d6a5751SDiogo Ivo 1576d6a5751SDiogo Ivo /* SR1.0 shutdown command to stop processing at firmware. 1586d6a5751SDiogo Ivo * Command format: 0x8101ss00, where 1596d6a5751SDiogo Ivo * - ss: sequence number. Currently not used by driver. 1606d6a5751SDiogo Ivo */ 1616d6a5751SDiogo Ivo #define ICSSG_SHUTDOWN_CMD_SR1 0x81010000 1626d6a5751SDiogo Ivo 1636d6a5751SDiogo Ivo /* SR1.0 pstate speed/duplex command to set speed and duplex settings 1646d6a5751SDiogo Ivo * in firmware. 1656d6a5751SDiogo Ivo * Command format: 0x8102ssPN, where 1666d6a5751SDiogo Ivo * - ss: sequence number. Currently not used by driver. 1676d6a5751SDiogo Ivo * - P: port number (for switch mode). 1686d6a5751SDiogo Ivo * - N: Speed/Duplex state: 1696d6a5751SDiogo Ivo * 0x0 - 10Mbps/Half duplex; 1706d6a5751SDiogo Ivo * 0x8 - 10Mbps/Full duplex; 1716d6a5751SDiogo Ivo * 0x2 - 100Mbps/Half duplex; 1726d6a5751SDiogo Ivo * 0xa - 100Mbps/Full duplex; 1736d6a5751SDiogo Ivo * 0xc - 1Gbps/Full duplex; 1746d6a5751SDiogo Ivo * NOTE: The above are the same value as bits [3..1](slice 0) 1756d6a5751SDiogo Ivo * or bits [7..5](slice 1) of RGMII CFG register. 1766d6a5751SDiogo Ivo */ 1776d6a5751SDiogo Ivo #define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1 0x81020000 1786d6a5751SDiogo Ivo 179e9b4ece7SMD Danish Anwar struct icssg_setclock_desc { 180e9b4ece7SMD Danish Anwar u8 request; 181e9b4ece7SMD Danish Anwar u8 restore; 182e9b4ece7SMD Danish Anwar u8 acknowledgment; 183e9b4ece7SMD Danish Anwar u8 cmp_status; 184e9b4ece7SMD Danish Anwar u32 margin; 185e9b4ece7SMD Danish Anwar u32 cyclecounter0_set; 186e9b4ece7SMD Danish Anwar u32 cyclecounter1_set; 187e9b4ece7SMD Danish Anwar u32 iepcount_set; 188e9b4ece7SMD Danish Anwar u32 rsvd1; 189e9b4ece7SMD Danish Anwar u32 rsvd2; 190e9b4ece7SMD Danish Anwar u32 CMP0_current; 191e9b4ece7SMD Danish Anwar u32 iepcount_current; 192e9b4ece7SMD Danish Anwar u32 difference; 193e9b4ece7SMD Danish Anwar u32 cyclecounter0_new; 194e9b4ece7SMD Danish Anwar u32 cyclecounter1_new; 195e9b4ece7SMD Danish Anwar u32 CMP0_new; 196e9b4ece7SMD Danish Anwar } __packed; 197e9b4ece7SMD Danish Anwar 198e9b4ece7SMD Danish Anwar #define ICSSG_CMD_POP_SLICE0 56 199e9b4ece7SMD Danish Anwar #define ICSSG_CMD_POP_SLICE1 60 200e9b4ece7SMD Danish Anwar 201e9b4ece7SMD Danish Anwar #define ICSSG_CMD_PUSH_SLICE0 57 202e9b4ece7SMD Danish Anwar #define ICSSG_CMD_PUSH_SLICE1 61 203e9b4ece7SMD Danish Anwar 204e9b4ece7SMD Danish Anwar #define ICSSG_RSP_POP_SLICE0 58 205e9b4ece7SMD Danish Anwar #define ICSSG_RSP_POP_SLICE1 62 206e9b4ece7SMD Danish Anwar 207e9b4ece7SMD Danish Anwar #define ICSSG_RSP_PUSH_SLICE0 56 208e9b4ece7SMD Danish Anwar #define ICSSG_RSP_PUSH_SLICE1 60 209e9b4ece7SMD Danish Anwar 210e9b4ece7SMD Danish Anwar #define ICSSG_TS_POP_SLICE0 59 211e9b4ece7SMD Danish Anwar #define ICSSG_TS_POP_SLICE1 63 212e9b4ece7SMD Danish Anwar 213e9b4ece7SMD Danish Anwar #define ICSSG_TS_PUSH_SLICE0 40 214e9b4ece7SMD Danish Anwar #define ICSSG_TS_PUSH_SLICE1 41 215e9b4ece7SMD Danish Anwar 216487f7323SMD Danish Anwar struct mgmt_cmd { 217487f7323SMD Danish Anwar u8 param; 218487f7323SMD Danish Anwar u8 seqnum; 219487f7323SMD Danish Anwar u8 type; 220487f7323SMD Danish Anwar u8 header; 221487f7323SMD Danish Anwar u32 cmd_args[3]; 222487f7323SMD Danish Anwar }; 223487f7323SMD Danish Anwar 224487f7323SMD Danish Anwar struct mgmt_cmd_rsp { 225487f7323SMD Danish Anwar u32 reserved; 226487f7323SMD Danish Anwar u8 status; 227487f7323SMD Danish Anwar u8 seqnum; 228487f7323SMD Danish Anwar u8 type; 229487f7323SMD Danish Anwar u8 header; 230487f7323SMD Danish Anwar u32 cmd_args[3]; 231487f7323SMD Danish Anwar }; 232487f7323SMD Danish Anwar 233e9b4ece7SMD Danish Anwar /* FDB FID_C2 flag definitions */ 234e9b4ece7SMD Danish Anwar /* Indicates host port membership.*/ 235e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0) 236e9b4ece7SMD Danish Anwar /* Indicates that MAC ID is connected to physical port 1 */ 237e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1) 238e9b4ece7SMD Danish Anwar /* Indicates that MAC ID is connected to physical port 2 */ 239e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2) 240e9b4ece7SMD Danish Anwar /* Ageable bit is set for learned entries and cleared for static entries */ 241e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_AGEABLE BIT(3) 242e9b4ece7SMD Danish Anwar /* If set for DA then packet is determined to be a special packet */ 243e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_BLOCK BIT(4) 244e9b4ece7SMD Danish Anwar /* If set for DA then the SA from the packet is not learned */ 245e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_SECURE BIT(5) 246e9b4ece7SMD Danish Anwar /* If set, it means packet has been seen recently with source address + FID 247e9b4ece7SMD Danish Anwar * matching MAC address/FID of entry 248e9b4ece7SMD Danish Anwar */ 249e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_TOUCHED BIT(6) 250e9b4ece7SMD Danish Anwar /* Set if entry is valid */ 251e9b4ece7SMD Danish Anwar #define ICSSG_FDB_ENTRY_VALID BIT(7) 252e9b4ece7SMD Danish Anwar 253e9b4ece7SMD Danish Anwar /** 254e9b4ece7SMD Danish Anwar * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM 255e9b4ece7SMD Danish Anwar * @fid_c1: membership and forwarding rules flag to this table. See 256e9b4ece7SMD Danish Anwar * above to defines for bit definitions 257e9b4ece7SMD Danish Anwar * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID) 258e9b4ece7SMD Danish Anwar */ 259e9b4ece7SMD Danish Anwar struct prueth_vlan_tbl { 260e9b4ece7SMD Danish Anwar u8 fid_c1; 261e9b4ece7SMD Danish Anwar u8 fid; 262e9b4ece7SMD Danish Anwar } __packed; 263e9b4ece7SMD Danish Anwar 264e9b4ece7SMD Danish Anwar /** 265e9b4ece7SMD Danish Anwar * struct prueth_fdb_slot - Result of FDB slot lookup 266e9b4ece7SMD Danish Anwar * @mac: MAC address 267e9b4ece7SMD Danish Anwar * @fid: fid to be associated with MAC 268e9b4ece7SMD Danish Anwar * @fid_c2: FID_C2 entry for this MAC 269e9b4ece7SMD Danish Anwar */ 270e9b4ece7SMD Danish Anwar struct prueth_fdb_slot { 271e9b4ece7SMD Danish Anwar u8 mac[ETH_ALEN]; 272e9b4ece7SMD Danish Anwar u8 fid; 273e9b4ece7SMD Danish Anwar u8 fid_c2; 274e9b4ece7SMD Danish Anwar } __packed; 275e9b4ece7SMD Danish Anwar 276e9b4ece7SMD Danish Anwar enum icssg_ietfpe_verify_states { 277e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_UNKNOWN = 0, 278e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_INITIAL, 279e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_VERIFYING, 280e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_SUCCEEDED, 281e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_FAILED, 282e9b4ece7SMD Danish Anwar ICSSG_IETFPE_STATE_DISABLED 283e9b4ece7SMD Danish Anwar }; 284e9b4ece7SMD Danish Anwar #endif /* __NET_TI_ICSSG_CONFIG_H */ 285