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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
78 #define WLAN_FC_STYPE_CFPOLL 6
99 #define WLAN_AUTH_FILS_PK 6
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
108 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
24 def immU6 : immU<6>;
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
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/freebsd/contrib/wpa/src/crypto/
H A Dmilenage.c2 * 3GPP AKA - Milenage algorithm (3GPP TS 35.205, .206, .207, .208)
3 * Copyright (c) 2006-2007 <j@w1.fi>
10 * EAP-AKA to be tested properly with real USIM cards.
26 * milenage_f1 - Milenage f1 and f1* algorithms
27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
93 * enum dpkg_extract_type - Enumeration for selecting extraction type
96 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -3
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(2)
12 #define BIT_FEN_BB_GLB_RST BIT(
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/sys/dev/clk/rockchip/
H A Drk3328_cru.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
62 #define ARMCLK 6
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_8.out11 6 0 64 1
15 be: 0 -1 00000000
16 is: 0 -1 00000000
34 6 0
38 be: 0 -1 00000000
39 is: 0 -1 00000000
46 be: 0 -1 00000000
47 is: 0 -1 00000000
50 be: 0 -1 00000000
51 is: 0 -1 00000000
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
40 if (rtwdev->chip->chip_ge in rtw89_get_data_ht_mcs()
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
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/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
203 /* Manage MAC address, read command - indirect (0x0107)
208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
209 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
210 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
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/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal_rx.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
245 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
246 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
247 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
298 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
299 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
302 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
303 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
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/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Dfloating-point.json3 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision float…
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …-bit packed computational double precision floating-point instructions retired; some instructions …
13 …"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision float…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …-bit packed computational single precision floating-point instructions retired; some instructions …
23 …"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision float…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-bit packed double computational precision floating-point instructions retired; some instructions …
33 …"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision float…
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
63 #define MT_TXD2_FIXED_RATE BIT(30)
67 #define MT_TXD2_HTC_VLD BIT(13)
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
25 #define ADF_C4XXX_SADB_BIT_OFFSET 6
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
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/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dfloating-point.json5 "Counter": "0,1,2,3,4,5,6,7",
9 "PEBScounters": "0,1,2,3,4,5,6,7",
16 "Counter": "0,1,2,3,4,5,6,7",
19 "PEBScounters": "0,1,2,3,4,5,6,7",
27 "Counter": "0,1,2,3,4,5,6,7",
30 "PEBScounters": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
40 "PEBScounters": "0,1,2,3,4,5,6,7",
47 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
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/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Dfloating-point.json5 "Counter": "0,1,2,3,4,5,6,7",
8 "PEBScounters": "0,1,2,3,4,5,6,7",
15 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
21 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
26 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
28 "Counter": "0,1,2,3,4,5,6,7",
31 "PEBScounters": "0,1,2,3,4,5,6,7",
32 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
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/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A Dfloating-point.json5 "Counter": "0,1,2,3,4,5,6,7",
8 "PEBScounters": "0,1,2,3,4,5,6,7",
15 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
21 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
26 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
28 "Counter": "0,1,2,3,4,5,6,7",
31 "PEBScounters": "0,1,2,3,4,5,6,7",
32 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
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/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A Dfloating-point.json5 "Counter": "0,1,2,3,4,5,6,7",
8 "PEBScounters": "0,1,2,3,4,5,6,7",
14 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
16 "Counter": "0,1,2,3,4,5,6,7",
19 "PEBScounters": "0,1,2,3,4,5,6,7",
20 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
25 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
27 "Counter": "0,1,2,3,4,5,6,7",
30 "PEBScounters": "0,1,2,3,4,5,6,7",
31 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
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