152d973f5SAlexander Motin[ 252d973f5SAlexander Motin { 352d973f5SAlexander Motin "BriefDescription": "Counts all microcode FP assists.", 452d973f5SAlexander Motin "CollectPEBSRecord": "2", 552d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 652d973f5SAlexander Motin "EventCode": "0xc1", 752d973f5SAlexander Motin "EventName": "ASSISTS.FP", 852d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 952d973f5SAlexander Motin "PublicDescription": "Counts all microcode Floating Point assists.", 1052d973f5SAlexander Motin "SampleAfterValue": "100003", 1152d973f5SAlexander Motin "UMask": "0x2" 1252d973f5SAlexander Motin }, 1352d973f5SAlexander Motin { 1452d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 1552d973f5SAlexander Motin "CollectPEBSRecord": "2", 1652d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 1752d973f5SAlexander Motin "EventCode": "0xc7", 1852d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 1952d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 20*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 2152d973f5SAlexander Motin "SampleAfterValue": "100003", 2252d973f5SAlexander Motin "UMask": "0x4" 2352d973f5SAlexander Motin }, 2452d973f5SAlexander Motin { 2552d973f5SAlexander Motin "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 2652d973f5SAlexander Motin "CollectPEBSRecord": "2", 2752d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 2852d973f5SAlexander Motin "EventCode": "0xc7", 2952d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 3052d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 31*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 3252d973f5SAlexander Motin "SampleAfterValue": "100003", 3352d973f5SAlexander Motin "UMask": "0x8" 3452d973f5SAlexander Motin }, 3552d973f5SAlexander Motin { 3652d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 3752d973f5SAlexander Motin "CollectPEBSRecord": "2", 3852d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 3952d973f5SAlexander Motin "EventCode": "0xc7", 4052d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 4152d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 42*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 4352d973f5SAlexander Motin "SampleAfterValue": "100003", 4452d973f5SAlexander Motin "UMask": "0x10" 4552d973f5SAlexander Motin }, 4652d973f5SAlexander Motin { 4752d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 4852d973f5SAlexander Motin "CollectPEBSRecord": "2", 4952d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 5052d973f5SAlexander Motin "EventCode": "0xc7", 5152d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 5252d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 53*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 5452d973f5SAlexander Motin "SampleAfterValue": "100003", 5552d973f5SAlexander Motin "UMask": "0x20" 5652d973f5SAlexander Motin }, 5752d973f5SAlexander Motin { 5852d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 5952d973f5SAlexander Motin "CollectPEBSRecord": "2", 6052d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 6152d973f5SAlexander Motin "EventCode": "0xc7", 6252d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 6352d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 64*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 6552d973f5SAlexander Motin "SampleAfterValue": "100003", 6652d973f5SAlexander Motin "UMask": "0x40" 6752d973f5SAlexander Motin }, 6852d973f5SAlexander Motin { 69*18054d02SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 7052d973f5SAlexander Motin "CollectPEBSRecord": "2", 7152d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 7252d973f5SAlexander Motin "EventCode": "0xc7", 7352d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 7452d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 75*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 7652d973f5SAlexander Motin "SampleAfterValue": "100003", 7752d973f5SAlexander Motin "UMask": "0x80" 7852d973f5SAlexander Motin }, 7952d973f5SAlexander Motin { 8052d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 8152d973f5SAlexander Motin "CollectPEBSRecord": "2", 8252d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 8352d973f5SAlexander Motin "EventCode": "0xc7", 8452d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 8552d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 86*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 8752d973f5SAlexander Motin "SampleAfterValue": "100003", 8852d973f5SAlexander Motin "UMask": "0x1" 8952d973f5SAlexander Motin }, 9052d973f5SAlexander Motin { 9152d973f5SAlexander Motin "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 9252d973f5SAlexander Motin "CollectPEBSRecord": "2", 9352d973f5SAlexander Motin "Counter": "0,1,2,3,4,5,6,7", 9452d973f5SAlexander Motin "EventCode": "0xc7", 9552d973f5SAlexander Motin "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 9652d973f5SAlexander Motin "PEBScounters": "0,1,2,3,4,5,6,7", 97*18054d02SAlexander Motin "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 9852d973f5SAlexander Motin "SampleAfterValue": "100003", 9952d973f5SAlexander Motin "UMask": "0x2" 10052d973f5SAlexander Motin } 10152d973f5SAlexander Motin]