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Searched +full:5 +full:vs2 (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td38 class RISCVLSUMOP<bits<5> val> {
39 bits<5> Value = val;
59 bits<5> uimm;
60 bits<5> rd;
76 bits<5> rs1;
77 bits<5> rd;
92 bits<5> rs2;
93 bits<5> rs1;
94 bits<5> rd;
110 bits<5> vs2;
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H A DRISCVInstrInfoV.td60 def simm5 : RISCVSImmLeafOp<5> {
64 return isInt<5>(Imm);
76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
336 // indexed load vd, (rs1), vs2, vm
340 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
341 "$vd, $rs1, $vs2$vm">;
362 // indexed segment load vd, (rs1), vs2, vm
367 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
[all …]
H A DRISCVInstrInfoZvk.td18 def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
35 bits<5> vs2;
37 bits<5> vd;
40 let Inst{31-27} = funct6{5-1};
41 let Inst{26} = imm{5};
43 let Inst{24-20} = vs2;
56 (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
57 opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
[all …]
H A DRISCVInstrInfoXTHead.td58 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
62 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
63 opcodestr, "$vd, $vs1, $vs2$vm"> {
68 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
73 opcodestr, "$vd, $rs1, $vs2$vm"> {
92 class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
107 class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
139 class THLoadPair<bits<5> funct5, string opcodestr>
153 class THStorePair<bits<5> funct5, string opcodestr>
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi84 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
243 pm8941_5vs2: 5vs2 {
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp522 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7)) in CheckLMUL()
745 CheckLMUL(TheCall, 5); in CheckBuiltinFunctionCall()
747 // bit_27_26, bit_11_7, vs2, simm5 in CheckBuiltinFunctionCall()
759 // bit_27_26, vs2, simm5 in CheckBuiltinFunctionCall()
768 // bit_27_26, vd, vs2, simm5 in CheckBuiltinFunctionCall()
776 CheckLMUL(TheCall, 5); in CheckBuiltinFunctionCall()
779 // bit_27_26, bit_11_7, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
789 // bit_27_26, vd, vs2, xs1 in CheckBuiltinFunctionCall()
794 // bit_27_26, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
803 // bit_27_26, vd, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
[all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c208 seq_printf(f, "%-8s %-16s %-5s %-12s %-12s %-12s " in spa_txg_history_show_header()
248 seq_printf(f, "%-8llu %-16llu %-5c %-12llu " in spa_txg_history_show()
433 vdev_get_stats(spa->spa_root_vdev, &ts->vs2); in spa_txg_history_fini_io()
438 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
439 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
440 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
441 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml55 lvs3, 5vs1, 5vs2
71 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
114 "^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
H A Dqcom,spmi-regulator.yaml39 "^(5vs[1-2]|(l|s)[1-9][0-9]?|lvs[1-4])$":
161 "^vdd_s[1-5]-supply$": true
220 "^vdd_s[1-5]-supply$": true
276 - description: Over-current protection interrupt for 5V S1
277 - description: Over-current protection interrupt for 5V S2
280 - const: ocp-5vs1
281 - const: ocp-5vs2
409 "^vdd_s[1-5]-supply$": true
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
270 l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186-corsola.dtsi209 pinctrl-5 = <&aud_dat_miso_on>;
417 it6505dptx: dp-bridge@5c {
1297 vsys-vs2-supply = <&pp4200_z2>;
1299 vs2-ldo1-supply = <&mt6366_vdram1_reg>;
1300 vs2-ldo2-supply = <&mt6366_vs2_reg>;
1301 vs2-ldo3-supply = <&mt6366_vs2_reg>;
1373 mt6366_vs2_reg: vs2 {
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td303 // Defines 5 instructions, unmasked, operand negating.
1064 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1083 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1086 v16i8:$vs3, v16i8:$vs2)),
1100 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1103 v16i8:$vs3, v16i8:$vs2)),
H A DPPCScheduleP7.td92 def P7_FXU_5C : SchedWriteRes<[P7_FXU]> { let Latency = 5; }
H A DPPCInstrP10.td123 let Inst{0-5} = pref;
136 let TSFlags{5-3} = PPC970_Unit;
152 class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
155 bits<5> VT;
156 bits<5> VB;
170 multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
187 bits<5> RST;
188 bits<5> RA;
209 bits<5> RT;
210 bits<5> RA;
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/freebsd/sys/contrib/openzfs/include/sys/
H A Dspa.h138 * 5 |G| offset3 |
202 * 5 | IV1 |
277 * 5 | payload |
446 #define BP_GET_LEVEL(bp) BF64_GET((bp)->blk_prop, 56, 5)
447 #define BP_SET_LEVEL(bp, x) BF64_SET((bp)->blk_prop, 56, 5, x)
925 TXG_STATE_COMMITTED = 5,
930 vdev_stat_t vs2; member
1164 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
1166 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
1168 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DPPC.cpp830 {{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"},
863 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},