Lines Matching +full:5 +full:vs2

18 def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
35   bits<5> vs2;
37   bits<5> vd;
40   let Inst{31-27} = funct6{5-1};
41   let Inst{26} = imm{5};
43   let Inst{24-20} = vs2;
56               (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
57               opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70                (ins VR:$vd, VR:$vs2, VR:$vs1),
71                opcodestr, "$vd, $vs2, $vs1"> {
77 // op vd, vs2, imm
84 // op vd, vs2, imm where vd is also a source regardless of tail policy
87                 (ins VR:$vd, VR:$vs2, optype:$imm),
88                 opcodestr, "$vd, $vs2, $imm"> {
95 // op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
97 class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
99     : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
100               opcodestr, "$vd, $vs2"> {
106 multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,