Lines Matching +full:5 +full:vs2

123   let Inst{0-5} = pref;
136   let TSFlags{5-3} = PPC970_Unit;
152 class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
155   bits<5> VT;
156   bits<5> VB;
170 multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
187   bits<5> RST;
188   bits<5> RA;
209   bits<5> RT;
210   bits<5> RA;
231   bits<5> RT;
261   bits<5> RST;
262   bits<5> RA;
281 class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
286   bits<5> RA;
300   let Inst{37} = XST{5};
311   bits<5> VRB;
312   bits<5> IMM;
319   let Inst{31} = XT{5};
348     let Inst{60} = XC{5};
349     let Inst{61} = XA{5};
350     let Inst{62} = XB{5};
351     let Inst{63} = XT{5};
357   bits<5> RD;
358   bits<5> VB;
390   bits<5> VA;
391   bits<5> VB;
407   bits<5> VRT;
408   bits<5> VRA;
409   bits<5> VRB;
425   bits<5> RD;
426   bits<5> VB;
459   let Inst{47} = XT{5};
486   let Inst{47} = XT{5};
512   let Inst{60} = XC{5};
513   let Inst{61} = XA{5};
514   let Inst{62} = XB{5};
515   let Inst{63} = XT{5};
543   let Inst{60} = XC{5};
544   let Inst{61} = XA{5};
545   let Inst{62} = XB{5};
546   let Inst{63} = XT{5};
550 class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
564   let Inst{30}    = XB{5};
572   bits<5> BI;
611 multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
851   bits<5> XTp;
852   bits<5> RA;
867   bits<5> XTp;
868   bits<5> RA;
869   bits<5> RB;
883   bits<5> XTp;
884   bits<5> RA;
922 class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
938 class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
942   bits<5> UIM;
950   let Inst{31} = XT{5};
968   let Inst{29}    = XA{5};
969   let Inst{30}    = XB{5};
1001   let Inst{61} = XA{5};
1002   let Inst{62} = XB{5};
1031   let Inst{61} = XA{5};
1032   let Inst{62} = XB{5};
1062   let Inst{61} = XA{5};
1063   let Inst{62} = XB{5};
1094   let Inst{61} = XA{5};
1095   let Inst{62} = XB{5};
1127   let Inst{61} = XA{5};
1128   let Inst{62} = XB{5};
1141       (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1917   def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
2496   def : InstAlias<"plwsync", (SYNCP10 5, 0)>;