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/linux/arch/arm64/crypto/
H A Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
17 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
21 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
33 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
37 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
41 .inst 0xce408c00 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
89 0: ld1 {v0.16b-v3.16b}, [x1], #64
95 CPU_LE( rev32 v0.16b, v0.16b )
[all …]
H A Daes-modes.S26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
35 #if MAX_STRIDE == 5
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
73 ld1 {v0.16b}, [x1], #16 /* get next pt block */
74 encrypt_block v0, w3, x2, x5, w6
75 st1 {v0.16b}, [x0], #16
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H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
23 .inst 0xcec08400 | (.L\vn << 5) | .L\vd
27 .inst 0xce60c800 | (.L\vm << 16) | (.L\vn << 5) | .L\vd
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
59 eor v0.16b, v0.16b, v1.16b;
61 sm4ekey v0.4s, v0.4s, v24.4s;
62 sm4ekey v1.4s, v0.4s, v25.4s;
73 st1 {v0.16b-v3.16b}, [x1], #64;
83 tbl v23.16b, {v0.16b}, v24.16b
[all …]
H A Dsha3-ce-core.S15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
46 ld1 { v0.1d- v3.1d}, [x0]
61 eor v0.8b, v0.8b, v25.8b
112 eor3 v25.16b, v0.16b, v5.16b, v10.16b
126 eor v0.16b, v0.16b, v30.16b
178 bcax v3.16b, v27.16b, v0.16b, v28.16b
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H A Daes-neonbs-core.S405 cmtst v0.16b, v7.16b, v8.16b
413 not v0.16b, v0.16b
437 eor v10.16b, v0.16b, v9.16b // xor with round0 key
439 tbl v0.16b, {v10.16b}, v8.16b
454 bitslice v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11
460 shift_rows v0, v1, v2, v3, v4, v5, v6, v7, v24
462 sbox v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, \
469 mix_cols v0, v1, v4, v6, v3, v7, v2, v5, v8, v9, v10, v11, v12, \
472 add_round_key v0, v1, v2, v3, v4, v5, v6, v7
481 bitslice v0, v1, v4, v6, v3, v7, v2, v5, v8, v9, v10, v11
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/linux/arch/mips/include/asm/mach-cavium-octeon/
H A Dkernel-entry-init.h30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
43 and v0, v0, v1
44 ori v0, v0, (6 << 7)
58 bnez t1, 5f # Skip WAR for others.
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/linux/lib/
H A Dsiphash.c20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
23 u64 v0 = SIPHASH_CONST_0; \
31 v0 ^= key->key[0];
37 v0 ^= b; \
43 return (v0 ^ v1) ^ (v2 ^ v3);
57 v0 ^= m; in __siphash_aligned()
66 case 6: b |= ((u64)end[5]) << 40; fallthrough; in __siphash_aligned()
67 case 5: b |= ((u64)end[4]) << 32; fallthrough; in __siphash_aligned()
90 v0 ^= m; in __siphash_unaligned()
99 case 6: b |= ((u64)end[5]) << 40; fallthrough; in __siphash_unaligned()
[all …]
/linux/arch/mips/kernel/
H A Dscall32-o32.S24 .align 5
61 load_a4: user_lw(t5, 16(t0)) # argument #5 from usp
67 sw t5, 16(sp) # argument #5 to ksp
81 * syscall number is in v0 unless we called syscall(__NR_###)
84 subu t2, v0, __NR_O32_Linux
89 LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
97 subu v0, v0, __NR_O32_Linux # check syscall number
98 sltiu t0, v0, __NR_O32_Linux_syscalls
101 sll t0, v0, 2
111 sltu t0, t0, v0
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H A Dscall64-o32.S27 .align 5
36 dsubu t0, v0, __NR_O32_Linux # check syscall number
43 move a1, v0
69 load_a4: lw a4, 16(t0) # argument #5 from usp
83 * absolute syscall number is in v0 unless we called syscall(__NR_###)
90 subu t2, v0, __NR_O32_Linux
95 LONG_S v0, TI_SYSCALL($28) # Save v0 as syscall number
104 dsll t0, v0, 3 # offset into table
110 sltu t0, t0, v0
115 dnegu v0 # error
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H A Dcps-vec.S79 mfc0 \dest, CP0_CONFIG, 5
145 move a0, v0
269 * Returns: pointer to struct core_boot_config in v0, pointer to
279 PTR_ADDU v0, t0, t1
318 PTR_L ta3, COREBOOTCFG_VPECONFIG(v0)
331 has_vp t0, 5f
353 has_mt t0, 5f
485 5: jr ra
504 mfc0 v0, CP0_CONFIG, 1
507 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
[all …]
H A Dscall64-n32.S25 .align 5
35 dsubu t0, v0, __NR_N32_Linux # check syscall number
47 LONG_S v0, TI_SYSCALL($28) # Store syscall number
55 dsll t0, v0, 3 # offset into table
61 sltu t0, t0, v0
66 dnegu v0 # error
68 1: sd v0, PT_R2(sp) # result
79 bltz v0, 1f # seccomp failed? Skip syscall
82 ld v0, PT_R2(sp) # Restore syscall (maybe modified)
90 dsubu t2, v0, __NR_N32_Linux # check (new) syscall number
H A Dscall64-n64.S27 .align 5
49 LONG_S v0, TI_SYSCALL($28) # Store syscall number
57 dsubu t2, v0, __NR_64_Linux
70 sltu t0, t0, v0
75 dnegu v0 # error
77 1: sd v0, PT_R2(sp) # result
89 bltz v0, 1f # seccomp failed? Skip syscall
92 ld v0, PT_R2(sp) # Restore syscall (maybe modified)
105 li v0, ENOSYS # error
106 sd v0, PT_R2(sp)
H A Docteon_switch.S87 move v0, a0
148 mfc0 v0, $15,0 /* Get the processor ID register */
153 beq v0, v1, 2f
161 subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
316 li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
318 bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
346 ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
400 subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
402 bltz v0, done_restore
468 sd $12, PT_MTP+(5*8)(sp) /* store P5 */
[all …]
/linux/arch/powerpc/lib/
H A Dmemcpy_power7.S62 blt 5f
81 .align 5
133 5: srdi r6,r5,4
300 bf cr7*4+3,5f
306 5: bf cr7*4+2,6f
308 lvx v0,r4,r9
311 stvx v0,r3,r9
318 lvx v0,r4,r11
323 stvx v0,r3,r11
344 .align 5
[all …]
H A Dcopyuser_power7.S118 blt 5f
137 .align 5
189 5: srdi r6,r5,4
354 bf cr7*4+3,5f
360 5: bf cr7*4+2,6f
362 err3; lvx v0,r4,r9
365 err3; stvx v0,r3,r9
372 err3; lvx v0,r4,r11
377 err3; stvx v0,r3,r11
398 .align 5
[all …]
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_power7.S62 blt 5f
81 .align 5
133 5: srdi r6,r5,4
300 bf cr7*4+3,5f
306 5: bf cr7*4+2,6f
308 lvx v0,r4,r9
311 stvx v0,r3,r9
318 lvx v0,r4,r11
323 stvx v0,r3,r11
344 .align 5
[all …]
H A Dcopyuser_power7.S118 blt 5f
137 .align 5
189 5: srdi r6,r5,4
354 bf cr7*4+3,5f
360 5: bf cr7*4+2,6f
362 err3; lvx v0,r4,r9
365 err3; stvx v0,r3,r9
372 err3; lvx v0,r4,r11
377 err3; stvx v0,r3,r11
398 .align 5
[all …]
/linux/include/uapi/linux/
H A Dpsci.h16 * PSCI v0.1 interface
18 * The PSCI v0.1 function numbers are implementation defined.
22 * to PSCI v0.1.
25 /* PSCI v0.2 interface */
38 #define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
47 #define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
74 /* PSCI v0.2 power state encoding for CPU_SUSPEND function */
91 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
96 /* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
136 #define PSCI_RET_ON_PENDING -5
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/linux/arch/x86/crypto/
H A Daes-xts-avx-x86_64.S112 // Define register aliases V0-V15, or V0-V31 if all 32 SIMD registers
120 _define_Vi 5
150 // V0-V3 hold the data blocks during the main loop, or temporary values
285 // store them in the vector registers TWEAK0-TWEAK3. Clobbers V0-V5.
309 vpsrlq $64 - 1*VL/16, TWEAK0, V0
312 vpclmulqdq $0x01, GF_POLY, V0, V1
315 vpslldq $8, V0, V0
322 vpternlogd $0x96, V0, V1, TWEAK1
326 vpxor V0, TWEAK1, TWEAK1
342 .elseif \i == 5
[all …]
H A Daes-gcm-avx10-x86_64.S141 // register aliases V0-V31 that map to the ymm or zmm registers.
144 .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \
271 .elseif \i == 5
287 .irp i, 0,1,2,3,4,5,6,7,8,9
333 // Additional local variables. V0-V2 and %rax are used as temporaries.
421 // [H^4, H^4, H^4, H^4] to get [H^(i+7), H^(i+6), H^(i+5), H^(i+4)].
425 _ghash_mul H_INC, H_CUR, H_CUR, GFPOLY, V0, V1, V2
466 // H_POW3*GHASHDATA1 => H^6*blk2 and H^5*blk3
510 .elseif \i == 5
511 vpternlogd $0x96, GHASHTMP2, GHASHTMP1, GHASHTMP0 // sum(MI_{6,5,4,3,2,1,0})
[all …]
/linux/arch/mips/include/asm/mach-malta/
H A Dkernel-entry-init.h83 mfc0 t0, $16, 5
86 mtc0 t0, $16, 5
113 PTR_LA v0, 0x9fc00534 /* YAMON print */
114 lw v0, (v0)
117 jal v0
119 PTR_LA v0, 0x9fc00520 /* YAMON exit */
120 lw v0, (v0)
122 jal v0
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dif0012.h41 } v0; member
80 } v0; member
89 } v0; member
98 } v0; member
116 } v0; member
138 } v0; member
150 } v0; member
157 } v0; member
165 } v0; member
179 } v0; member
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm167 var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5
391 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)
533 // Save v0 by itself since it requires only two SGPRs.
538 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] V_COHERENCE
539 v_mov_b32 v0, 0x0
556 v_writelane_b32 v0, ttmp4, 0x4
557 v_writelane_b32 v0, ttmp5, 0x5
558 v_writelane_b32 v0, ttmp6, 0x6
559 v_writelane_b32 v0, ttmp7, 0x7
560 v_writelane_b32 v0, ttmp8, 0x8
[all …]
/linux/arch/alpha/lib/
H A Dstrrchr.S29 andnot a0, 7, v0 # .. e1 : align source addr
45 ldq t0, 8(v0) # e0 : load next quadword
46 cmovne t3, v0, t6 # .. e1 : save previous comparisons match
48 addq v0, 8, v0 # .. e1 :
63 cmovne t3, v0, t6 # e0 :
68 is 5 cycles -- the same as just falling through. */
80 addq t6, t0, v0 # .. e1 : add our aligned base ptr to the mix
81 addq v0, t1, v0 # e0 :
85 mov zero, v0 # e0 :
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmgp100.c186 VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes); in gp100_vmm_lpt_invalid()
386 { LPT, 5, 8, 0x0100, &gp100_vmm_desc_lpt },
412 struct gp100_vmm_map_v0 v0; in gp100_vmm_valid() member
423 if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) { in gp100_vmm_valid()
424 vol = !!args->v0.vol; in gp100_vmm_valid()
425 ro = !!args->v0.ro; in gp100_vmm_valid()
426 priv = !!args->v0.priv; in gp100_vmm_valid()
427 kind = args->v0.kind; in gp100_vmm_valid()
479 map->type |= (u64)priv << 5; in gp100_vmm_valid()
490 struct gp100_vmm_fault_cancel_v0 v0; in gp100_vmm_fault_cancel() member
[all …]

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