16f52b16cSGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2e546eea7SAnup Patel /* 3e546eea7SAnup Patel * ARM Power State and Coordination Interface (PSCI) header 4e546eea7SAnup Patel * 5e546eea7SAnup Patel * This header holds common PSCI defines and macros shared 6e546eea7SAnup Patel * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. 7e546eea7SAnup Patel * 8e546eea7SAnup Patel * Copyright (C) 2014 Linaro Ltd. 9e546eea7SAnup Patel * Author: Anup Patel <anup.patel@linaro.org> 10e546eea7SAnup Patel */ 11e546eea7SAnup Patel 12e546eea7SAnup Patel #ifndef _UAPI_LINUX_PSCI_H 13e546eea7SAnup Patel #define _UAPI_LINUX_PSCI_H 14e546eea7SAnup Patel 15e546eea7SAnup Patel /* 16e546eea7SAnup Patel * PSCI v0.1 interface 17e546eea7SAnup Patel * 18e546eea7SAnup Patel * The PSCI v0.1 function numbers are implementation defined. 19e546eea7SAnup Patel * 20e546eea7SAnup Patel * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, 21e546eea7SAnup Patel * INVALID_PARAMS, and DENIED defined below are applicable 22e546eea7SAnup Patel * to PSCI v0.1. 23e546eea7SAnup Patel */ 24e546eea7SAnup Patel 25e546eea7SAnup Patel /* PSCI v0.2 interface */ 26e546eea7SAnup Patel #define PSCI_0_2_FN_BASE 0x84000000 27e546eea7SAnup Patel #define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) 28e546eea7SAnup Patel #define PSCI_0_2_64BIT 0x40000000 29e546eea7SAnup Patel #define PSCI_0_2_FN64_BASE \ 30e546eea7SAnup Patel (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) 31e546eea7SAnup Patel #define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) 32e546eea7SAnup Patel 33e546eea7SAnup Patel #define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) 34e546eea7SAnup Patel #define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) 35e546eea7SAnup Patel #define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) 36e546eea7SAnup Patel #define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) 37e546eea7SAnup Patel #define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) 38e546eea7SAnup Patel #define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) 39e546eea7SAnup Patel #define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) 40e546eea7SAnup Patel #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) 41e546eea7SAnup Patel #define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) 42e546eea7SAnup Patel #define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) 43e546eea7SAnup Patel 44e546eea7SAnup Patel #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) 45e546eea7SAnup Patel #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) 46e546eea7SAnup Patel #define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) 47e546eea7SAnup Patel #define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) 48e546eea7SAnup Patel #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) 49e546eea7SAnup Patel 505f004e0cSLorenzo Pieralisi #define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10) 513137f2e6SDmitry Baryshkov #define PSCI_1_0_FN_CPU_FREEZE PSCI_0_2_FN(11) 523137f2e6SDmitry Baryshkov #define PSCI_1_0_FN_CPU_DEFAULT_SUSPEND PSCI_0_2_FN(12) 533137f2e6SDmitry Baryshkov #define PSCI_1_0_FN_NODE_HW_STATE PSCI_0_2_FN(13) 54faf7ec4aSSudeep Holla #define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14) 5560dd1eadSUlf Hansson #define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15) 563137f2e6SDmitry Baryshkov #define PSCI_1_0_FN_STAT_RESIDENCY PSCI_0_2_FN(16) 573137f2e6SDmitry Baryshkov #define PSCI_1_0_FN_STAT_COUNT PSCI_0_2_FN(17) 58faf7ec4aSSudeep Holla 593137f2e6SDmitry Baryshkov #define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) 603137f2e6SDmitry Baryshkov #define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19) 61*f3dc61cdSWill Deacon #define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(20) 623137f2e6SDmitry Baryshkov 633137f2e6SDmitry Baryshkov #define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12) 643137f2e6SDmitry Baryshkov #define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13) 65faf7ec4aSSudeep Holla #define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14) 663137f2e6SDmitry Baryshkov #define PSCI_1_0_FN64_STAT_RESIDENCY PSCI_0_2_FN64(16) 673137f2e6SDmitry Baryshkov #define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17) 683137f2e6SDmitry Baryshkov 694302e381SSudeep Holla #define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) 70*f3dc61cdSWill Deacon #define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(20) 715f004e0cSLorenzo Pieralisi 72e546eea7SAnup Patel /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ 73e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff 74e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_ID_SHIFT 0 75e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 76e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_TYPE_MASK \ 77e546eea7SAnup Patel (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) 78e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 79e546eea7SAnup Patel #define PSCI_0_2_POWER_STATE_AFFL_MASK \ 80e546eea7SAnup Patel (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) 81e546eea7SAnup Patel 82a5c00bb2SLorenzo Pieralisi /* PSCI extended power state encoding for CPU_SUSPEND function */ 83a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_EXT_POWER_STATE_ID_MASK 0xfffffff 84a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT 0 85a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT 30 86a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_EXT_POWER_STATE_TYPE_MASK \ 87a5c00bb2SLorenzo Pieralisi (0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT) 88a5c00bb2SLorenzo Pieralisi 89e546eea7SAnup Patel /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ 90e546eea7SAnup Patel #define PSCI_0_2_AFFINITY_LEVEL_ON 0 91e546eea7SAnup Patel #define PSCI_0_2_AFFINITY_LEVEL_OFF 1 92e546eea7SAnup Patel #define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 93e546eea7SAnup Patel 94e546eea7SAnup Patel /* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ 95e546eea7SAnup Patel #define PSCI_0_2_TOS_UP_MIGRATE 0 96e546eea7SAnup Patel #define PSCI_0_2_TOS_UP_NO_MIGRATE 1 97e546eea7SAnup Patel #define PSCI_0_2_TOS_MP 2 98e546eea7SAnup Patel 99d43583b8SWill Deacon /* PSCI v1.1 reset type encoding for SYSTEM_RESET2 */ 100d43583b8SWill Deacon #define PSCI_1_1_RESET_TYPE_SYSTEM_WARM_RESET 0 101d43583b8SWill Deacon #define PSCI_1_1_RESET_TYPE_VENDOR_START 0x80000000U 102d43583b8SWill Deacon 103e546eea7SAnup Patel /* PSCI version decoding (independent of PSCI version) */ 104e546eea7SAnup Patel #define PSCI_VERSION_MAJOR_SHIFT 16 105e546eea7SAnup Patel #define PSCI_VERSION_MINOR_MASK \ 106e546eea7SAnup Patel ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) 107e546eea7SAnup Patel #define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK 108e546eea7SAnup Patel #define PSCI_VERSION_MAJOR(ver) \ 109e546eea7SAnup Patel (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) 110e546eea7SAnup Patel #define PSCI_VERSION_MINOR(ver) \ 111e546eea7SAnup Patel ((ver) & PSCI_VERSION_MINOR_MASK) 112d0a144f1SMarc Zyngier #define PSCI_VERSION(maj, min) \ 113d0a144f1SMarc Zyngier ((((maj) << PSCI_VERSION_MAJOR_SHIFT) & PSCI_VERSION_MAJOR_MASK) | \ 114d0a144f1SMarc Zyngier ((min) & PSCI_VERSION_MINOR_MASK)) 115e546eea7SAnup Patel 116a5c00bb2SLorenzo Pieralisi /* PSCI features decoding (>=1.0) */ 117a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT 1 118a5c00bb2SLorenzo Pieralisi #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK \ 119a5c00bb2SLorenzo Pieralisi (0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT) 120a5c00bb2SLorenzo Pieralisi 12160dd1eadSUlf Hansson #define PSCI_1_0_OS_INITIATED BIT(0) 12260dd1eadSUlf Hansson #define PSCI_1_0_SUSPEND_MODE_PC 0 12360dd1eadSUlf Hansson #define PSCI_1_0_SUSPEND_MODE_OSI 1 12460dd1eadSUlf Hansson 125e546eea7SAnup Patel /* PSCI return values (inclusive of all PSCI versions) */ 126e546eea7SAnup Patel #define PSCI_RET_SUCCESS 0 127e546eea7SAnup Patel #define PSCI_RET_NOT_SUPPORTED -1 128e546eea7SAnup Patel #define PSCI_RET_INVALID_PARAMS -2 129e546eea7SAnup Patel #define PSCI_RET_DENIED -3 130e546eea7SAnup Patel #define PSCI_RET_ALREADY_ON -4 131e546eea7SAnup Patel #define PSCI_RET_ON_PENDING -5 132e546eea7SAnup Patel #define PSCI_RET_INTERNAL_FAILURE -6 133e546eea7SAnup Patel #define PSCI_RET_NOT_PRESENT -7 134e546eea7SAnup Patel #define PSCI_RET_DISABLED -8 1352217d7c6SLorenzo Pieralisi #define PSCI_RET_INVALID_ADDRESS -9 136e546eea7SAnup Patel 137e546eea7SAnup Patel #endif /* _UAPI_LINUX_PSCI_H */ 138