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/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S3 * Serpent Cipher 4-way parallel algorithm (i586/SSE2)
17 #define arg_ctx 4
23 4-way SSE2 serpent
39 movd (4*(i)+(j))*4(CTX), t; \
42 #define K(x0, x1, x2, x3, x4, i) \ argument
48 pxor RT1, x2; \
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
58 movdqa x2, x4; \
59 pslld $3, x2; \
61 por x4, x2; \
[all …]
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
45 pxor x2, x4; \
50 pxor x0, x2;
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
54 pxor x2, x0; \
55 pand x1, x2; \
56 pxor x2, x3; \
58 pxor x4, x2; \
59 pxor x2, x1;
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
/linux/sound/soc/codecs/
H A Drt1318.h101 #define RT1318_PLLIN_MASK (0x7 << 4)
102 #define RT1318_PLLIN_BCLK0 (0x0 << 4)
103 #define RT1318_PLLIN_BCLK1 (0x1 << 4)
104 #define RT1318_PLLIN_RC (0x2 << 4)
105 #define RT1318_PLLIN_MCLK (0x3 << 4)
106 #define RT1318_PLLIN_SDW1 (0x4 << 4)
107 #define RT1318_PLLIN_SDW2 (0x5 << 4)
108 #define RT1318_PLLIN_SDW3 (0x6 << 4)
109 #define RT1318_PLLIN_SDW4 (0x7 << 4)
113 #define RT1318_SYSCLK_PLL2F (0x2 << 0)
[all …]
H A Dtscs454.h17 #define R_IRQEN VIRT_ADDR(0x0, 0x2)
69 #define R_HSDCTL2 VIRT_ADDR(0x1, 0x2)
100 #define R_DACCTL VIRT_ADDR(0x2, 0x1)
101 #define R_SPKCTL VIRT_ADDR(0x2, 0x2)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
103 #define R_DCCTL VIRT_ADDR(0x2, 0x4)
104 #define R_OVOLCTLU VIRT_ADDR(0x2, 0x6)
105 #define R_MUTEC VIRT_ADDR(0x2, 0x7)
106 #define R_MVOLL VIRT_ADDR(0x2, 0x8)
107 #define R_MVOLR VIRT_ADDR(0x2, 0x9)
[all …]
H A Drk3308_codec.h116 #define RK3308_DAC_MCLK_GATING BIT(4)
126 #define RK3308_ADC_I2S_VALID_LEN_24BITS (0x2 << RK3308_ADC_I2S_VALID_LEN_SFT)
132 #define RK3308_ADC_I2S_MODE_I2S (0x2 << RK3308_ADC_I2S_MODE_SFT)
140 #define RK3308_ADC_MODE_MASTER BIT(4)
144 #define RK3308_ADC_I2S_FRAME_24BITS (0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT)
154 #define RK3308_ADC_L_CH_BIST_CUBE (0x2 << RK3308_ADC_L_CH_BIST_SFT)
160 #define RK3308_ADC_R_CH_BIST_CUBE (0x2 << RK3308_ADC_R_CH_BIST_SFT)
168 #define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT)
173 #define RK3308_ADCL_DATA_SFT 4
183 #define RK3308_CTRL_GEN_SFT 4
[all …]
H A Dtas5720.h51 #define TAS5720_SAIF_RIGHTJ_18BIT (0x2)
59 #define TAS5720_MUTE BIT(4)
67 #define TAS5720_PWM_RATE_6_3_FSYNC (0x0 << 4)
68 #define TAS5720_PWM_RATE_8_4_FSYNC (0x1 << 4)
69 #define TAS5720_PWM_RATE_10_5_FSYNC (0x2 << 4)
70 #define TAS5720_PWM_RATE_12_6_FSYNC (0x3 << 4)
71 #define TAS5720_PWM_RATE_14_7_FSYNC (0x4 << 4)
72 #define TAS5720_PWM_RATE_16_8_FSYNC (0x5 << 4)
73 #define TAS5720_PWM_RATE_20_10_FSYNC (0x6 << 4)
74 #define TAS5720_PWM_RATE_24_12_FSYNC (0x7 << 4)
[all …]
H A Dtas2552.h43 #define TAS2552_PLL_SRC_MCLK (0x0 << 4)
44 #define TAS2552_PLL_SRC_BCLK (0x1 << 4)
45 #define TAS2552_PLL_SRC_IVCLKIN (0x2 << 4)
46 #define TAS2552_PLL_SRC_1_8_FIXED (0x3 << 4)
60 #define TAS2552_WCLK_FREQ_16KHZ (0x2 << 0)
69 #define TAS2552_DIN_SRC_SEL_RIGHT (0x2 << 3)
81 #define TAS2552_WORDLENGTH_24BIT (0x2 << 0)
86 #define TAS2552_DATAFORMAT_RIGHT_J (0x2 << 2)
89 #define TAS2552_CLKSPERFRAME_32 (0x0 << 4)
90 #define TAS2552_CLKSPERFRAME_64 (0x1 << 4)
[all …]
/linux/arch/arm64/crypto/
H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
19 .set .Lv\b\().4s, \b
47 * x2: rkey_dec
61 sm4ekey v0.4s, v0.4s, v24.4s;
62 sm4ekey v1.4s, v0.4s, v25.4s;
63 sm4ekey v2.4s, v1.4s, v26.4s;
64 sm4ekey v3.4s, v2.4s, v27.4s;
65 sm4ekey v4.4s, v3.4s, v28.4s;
66 sm4ekey v5.4s, v4.4s, v29.4s;
67 sm4ekey v6.4s, v5.4s, v30.4s;
[all …]
H A Dsm4-neon-core.S41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
52 zip1 RTMP1.4s, s2.4s, s3.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
54 zip2 RTMP3.4s, s2.4s, s3.4s; \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
56 zip1 RTMP5.4s, s6.4s, s7.4s; \
[all …]
/linux/tools/testing/selftests/arm64/abi/
H A Dsyscall-abi-asm.S27 #define ID_AA64SMFR0_EL1_SMEver_WIDTH 4
85 adrp x2, svcr_in
86 ldr x2, [x2, :lo12:svcr_in]
87 msr S3_3_C4_C2_2, x2
90 tbz x2, #SVCR_ZA_SHIFT, load_gpr
92 ldr x2, =za_in
94 add x2, x2, x1
100 mrs x2, S3_0_C0_C4_5 // ID_AA64SMFR0_EL1
101 ubfx x2, x2, #ID_AA64SMFR0_EL1_SMEver_SHIFT, \
103 cbz x2, load_gpr
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun9i-a80.c24 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
30 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
36 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
42 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
48 SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
50 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
54 SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
60 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
66 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
[all …]
H A Dpinctrl-sun50i-h616.c22 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */
28 SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */
34 SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */
40 SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
46 SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */
47 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
51 SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */
57 SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */
63 SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */
[all …]
H A Dpinctrl-sun8i-a23.c28 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
34 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
40 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
46 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
52 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
53 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
57 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
62 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
67 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
[all …]
H A Dpinctrl-sun50i-h6.c17 SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
19 SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
21 SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
23 SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
24 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
25 SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
27 SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
29 SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
31 SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
33 SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
[all …]
H A Dpinctrl-sun8i-a33.c27 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
33 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
39 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
44 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
49 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
51 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
55 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
61 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
67 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
[all …]
H A Dpinctrl-sun8i-a83t.c27 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
33 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
39 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
45 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
51 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
53 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
57 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
63 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
69 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
[all …]
H A Dpinctrl-sun50i-a64.c26 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
32 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
39 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
54 SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
57 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
61 SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
68 SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
75 SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
[all …]
H A Dpinctrl-sun8i-h3.c26 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
32 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
38 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
44 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
50 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
51 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
55 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
61 SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
66 SUNXI_FUNCTION(0x2, "sim"), /* CLK */
[all …]
/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh13 exit 4 # ksft_skip
224 " C0-1:P1 . . C2-3 C4-5 . . . 0 A1:4-5"
225 " C0-1:P1 . . C2-3 S+:C4-5 . . . 0 A1:4-5"
227 " C0-1 . . C2-3:P1 . . . C4-5 0 B1:4-5"
232 "C2-3:P1:S+ C2:P1 . . C2-4 . . . 0 A1:3-4|A2:2"
267 " C0-3:S+ C1-3:S+ C2-3 . X2-3 . . . 0 A1:0-3|A2:1-3|A3:2-3|XA1:2-3"
268 …" C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3:P2 . . 0 A1:0-1|A2:2-3|A3:2-3 A1:P0|A2:P2 2-…
269 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X3:P2 . . 0 A1:0-2|A2:3|A3:3 A1:P0|A2:P2 3"
270 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3 X2-3:P2 . 0 A1:0-1|A2:1|A3:2-3 A1:P0|A3:P2 2-3"
271 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3 X2-3:P2:C3 . 0 A1:0-1|A2:1|A3:2-3 A1:P0|A3:P2 2-3"
[all …]
/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h62 #define ATV_COMM_EXEC_HOLD 0x2
108 #define ATV_TOP_COMM_EXEC_HOLD 0x2
129 #define ATV_TOP_COMM_MB_OBS__M 0x2
133 #define ATV_TOP_COMM_MB_MUX_CTRL__W 4
147 #define ATV_TOP_COMM_MB_MUX_OBS__W 4
176 #define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2
196 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2
216 #define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2
277 #define ATV_TOP_NOISE_TH__W 4
346 #define ATV_TOP_MOD_CONTROL_MOD_IF__W 4
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts34 0x2 0x0 0x0 0xf0000000 0x04000000
91 pib@4,0 {
93 reg = <4 0 0x8000>;
143 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
144 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
145 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
148 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
149 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
150 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
151 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
[all …]
H A Dp1025rdb.dtsi102 /* 4MB for Linux Kernel Image */
108 /* 4MB for Compressed Root file System Image */
158 /* 4MB for Linux Kernel Image */
164 /* 4MB for Compressed RFS Image */
253 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
254 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
255 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
256 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
257 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
258 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
[all …]
/linux/arch/arm64/kvm/hyp/
H A Dentry.S29 adr_this_cpu x1, kvm_hyp_ctxt, x2
35 save_sp_el0 x1, x2
56 set_loaded_vcpu x0, x1, x2
61 mte_switch_to_guest x29, x1, x2
68 ptrauth_switch_to_guest x29, x0, x1, x2
75 ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)]
76 ldp x4, x5, [x29, #CPU_XREG_OFFSET(4)]
92 // x2-x29,lr: vcpu regs
100 // x2-x29,lr: vcpu regs
124 // x2-x29,lr: vcpu regs
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h29 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
34 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
38 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
48 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
53 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
58 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
63 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
68 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
[all …]
/linux/include/soc/fsl/qe/
H A Dimmap_qe.h61 u8 res1[0x2];
70 u8 res3[0x2];
73 u8 res5[0x2];
75 u8 res6[0x2];
77 u8 res7[0x2];
79 u8 res8[0x2];
81 u8 res9[0x2];
83 u8 res10[0x2];
84 __be16 ceexe4; /* QE external request 4 event register */
85 u8 res11[0x2];
[all …]

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