Lines Matching +full:4 +full:x2
17 SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
19 SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
21 SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
23 SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
24 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
25 SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
27 SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
29 SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
31 SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
33 SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
35 SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */
38 SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
41 SUNXI_FUNCTION(0x2, "ccir"), /* DE */
44 SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */
47 SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
50 SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */
51 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
53 SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */
56 SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */
59 SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */
62 SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */
65 SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */
68 SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */
71 SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */
74 SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */
78 SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
82 SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */
86 SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */
90 SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */
94 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
97 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
100 SUNXI_FUNCTION(0x2, "pwm1"),
109 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
114 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
119 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
124 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
126 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
129 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
134 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
140 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
152 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
157 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
162 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
167 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
172 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
177 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
182 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
187 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
191 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
196 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
203 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
210 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
217 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
224 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
231 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
238 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
252 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
259 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
266 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
273 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
287 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
294 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
301 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
308 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
314 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
320 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
326 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
333 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
346 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
352 SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
359 SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
366 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
373 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
381 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
387 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
393 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
399 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
405 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
407 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
411 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
422 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
427 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
432 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
437 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
442 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
443 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
447 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
452 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
457 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
462 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
468 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
474 SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
481 SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
488 SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
495 SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
502 SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
510 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
518 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
526 SUNXI_FUNCTION(0x2, "ir_tx"),
534 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
542 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
546 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */
550 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
558 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
571 SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
576 SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
581 SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
590 .irq_banks = 4,