Lines Matching +full:4 +full:x2
17 #define R_IRQEN VIRT_ADDR(0x0, 0x2)
69 #define R_HSDCTL2 VIRT_ADDR(0x1, 0x2)
100 #define R_DACCTL VIRT_ADDR(0x2, 0x1)
101 #define R_SPKCTL VIRT_ADDR(0x2, 0x2)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
103 #define R_DCCTL VIRT_ADDR(0x2, 0x4)
104 #define R_OVOLCTLU VIRT_ADDR(0x2, 0x6)
105 #define R_MUTEC VIRT_ADDR(0x2, 0x7)
106 #define R_MVOLL VIRT_ADDR(0x2, 0x8)
107 #define R_MVOLR VIRT_ADDR(0x2, 0x9)
108 #define R_HPVOLL VIRT_ADDR(0x2, 0x0A)
109 #define R_HPVOLR VIRT_ADDR(0x2, 0x0B)
110 #define R_SPKVOLL VIRT_ADDR(0x2, 0x0C)
111 #define R_SPKVOLR VIRT_ADDR(0x2, 0x0D)
112 #define R_SUBVOL VIRT_ADDR(0x2, 0x10)
113 #define R_COP0 VIRT_ADDR(0x2, 0x11)
114 #define R_COP1 VIRT_ADDR(0x2, 0x12)
115 #define R_COPSTAT VIRT_ADDR(0x2, 0x13)
116 #define R_PWM0 VIRT_ADDR(0x2, 0x14)
117 #define R_PWM1 VIRT_ADDR(0x2, 0x15)
118 #define R_PWM2 VIRT_ADDR(0x2, 0x16)
119 #define R_PWM3 VIRT_ADDR(0x2, 0x17)
120 #define R_HPSW VIRT_ADDR(0x2, 0x18)
121 #define R_THERMTS VIRT_ADDR(0x2, 0x19)
122 #define R_THERMSPK1 VIRT_ADDR(0x2, 0x1A)
123 #define R_THERMSTAT VIRT_ADDR(0x2, 0x1B)
124 #define R_SCSTAT VIRT_ADDR(0x2, 0x1C)
125 #define R_SDMON VIRT_ADDR(0x2, 0x1D)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
180 #define R_DACCRWDL VIRT_ADDR(0x4, 0x2)
233 #define R_SUBCRWDL VIRT_ADDR(0x5, 0x2)
328 #define FB_I2SPCTL_LRCLKP 4
344 #define FV_FORMAT_I2S 0x2
371 #define FV_I2SMBM_1 0x2
381 #define FM_PCMPCTL0_SLSYNCP 0x2
383 #define FV_SLSYNCP_LONG 0x2
406 #define FM_PCMPCTL1_PCMMIMP 0x2
414 #define FB_CHAIC_MICBST 4
541 #define FB_IRQEN_HSDINTEN 4
552 #define FM_IRQEN_GPIO3INTEN 0x2
553 #define FV_GPIO3INTEN_ENABLED 0x2
575 #define FB_IRQMASK_HSDIM 4
586 #define FM_IRQMASK_GPIO3M 0x2
588 #define FV_GPIO3M_NOT_MASKED 0x2
609 #define FB_IRQSTAT_HSDINT 4
620 #define FM_IRQSTAT_GPIO3INT 0x2
621 #define FV_GPIO3INT_INTERRUPTED 0x2
645 #define FB_DEVREV_MAJ_REV 4
653 #define FM_PLLSTAT_PLL2LK 0x2
654 #define FV_PLL2LK_LOCKED 0x2
681 #define FB_PLLCTL_PLL1CLKEN 4
696 #define FV_PLLISEL_MCLK2 0x2
714 #define FV_IBM_1 0x2
724 #define FB_SCLKCTL_DSDM 4
735 #define FB_I2SCMC_BCMP3 4
753 #define FV_BCMP1_40X 0x2
758 #define I2SCMC_BCMP_40X 0x2
762 #define FB_MCLK2PINC_SLEWOUT 4
774 #define FV_MCLK2OS_PLL2 0x2
790 #define FM_I2SPINC0_PCM2TRI 0x2
800 #define FM_I2SPINC1_SDO2PDD 0x2
809 #define FB_I2SPINC2_BC3PDD 4
819 #define FM_I2SPINC2_LR1PDD 0x2
834 #define FB_GPIOCTL0_GPIO2CFG 4
844 #define FM_GPIOCTL0_GPIO1IO 0x2
859 #define FB_GPIOCTL1_GPIO0 4
869 #define FM_GPIOCTL1_GPIO1RD 0x2
886 #define FB_ASRC_ASRCIB 4
904 #define FM_TDMCTL0_SLSYNC 0x2
906 #define FV_SLSYNC_LONG 0x2
930 #define FV_TDMSI_6 0x2
939 #define FB_PWRM0_INPROC1PU 4
949 #define FM_PWRM0_MICB1PU 0x2
964 #define FB_PWRM1_SPKLPU 4
974 #define FM_PWRM1_D2S1PU 0x2
985 #define FB_PWRM2_I2S2OPU 4
1001 #define FM_PWRM2_I2S2IPU 0x2
1003 #define FV_I2S2IPU_PWR_UP 0x2
1026 #define FB_PWRM3_LLINEPU 4
1033 #define FB_PWRM4_OPSUBPU 4
1043 #define FM_PWRM4_OPSPKLPU 0x2
1049 #define FB_I2SIDCTL_I2SI3DCTL 4
1059 #define FB_I2SODCTL_I2SO3DCTL 4
1091 #define FV_I2S1MUX_I2S3 0x2
1100 #define AUDIOMUX1_I2SMUX_I2S3 0x2
1130 #define FV_I2S3MUX_I2S3 0x2
1163 #define FV_CLSSDMUX_I2S3 0x2
1177 #define FB_HSDCTL1_DETCYC 4
1187 #define FM_HSDCTL1_HPID_EN 0x2
1201 #define FB_HSDCTL2_FORCETRG 4
1250 #define FB_CH0AIC_MICBST0 4
1257 #define FM_CH0AIC_IN_BYPS_L_SEL 0x2
1266 #define FB_CH1AIC_MICBST1 4
1273 #define FM_CH1AIC_IN_BYPS_R_SEL 0x2
1285 #define FB_ICTL0_INPCH10SEL 4
1295 #define FM_ICTL0_IN1HP 0x2
1307 #define FB_ICTL1_INPCH32SEL 4
1317 #define FM_ICTL1_IN3HP 0x2
1323 #define FB_MICBIAS_MICBOV2 4
1337 #define FM_PGAZ_INHPOR 0x2
1366 #define FM_IVOLCTLU_PGAVOLU 0x2
1375 #define FB_ALCCTL0_ALCREF 4
1385 #define FM_ALCCTL0_ALCEN1 0x2
1391 #define FB_ALCCTL1_MAXGAIN 4
1401 #define FB_ALCCTL2_MINGAIN 4
1408 #define FB_ALCCTL3_DCY 4
1431 #define FB_DMICCTL_DMONO 4
1451 #define FB_DACCTL_DACDITH 4
1503 #define FM_SUBCTL_SUBMUX 0x2
1522 #define FB_OVOLCTLU_OFADE 4
1532 #define FM_OVOLCTLU_SPKVOLU 0x2
1541 #define FB_MUTEC_ZDLEN 4
1628 #define FB_PWM1_DITHPOS 4
1632 #define FM_PWM1_DYNDITH 0x2
1646 #define FB_HPSW_HPDETSTATE 4
1653 #define FM_HPSW_HPSWPOL 0x2
1665 #define FB_THERMTS_TRIPSPLIT 4
1681 #define FB_THERMSPK1_INCRATIO 4
1720 #define FB_SPKEQFILT_EQ2BE 4
1773 #define FM_SPKMBCEN_MBCEN2 0x2
1774 #define FV_MBCEN2_ENABLE 0x2
1789 #define FB_SPKMBCCTL_WINSEL3 4
1799 #define FM_SPKMBCCTL_LVLMODE1 0x2
1805 #define FB_SPKCLECTL_LVLMODE 4
1817 #define FM_SPKCLECTL_LIMEN 0x2
1818 #define FV_LIMEN_ENABLE 0x2
1903 #define FB_SPKFXCTL_3DEN 4
1913 #define FM_SPKFXCTL_BEEN 0x2
1924 #define FB_DACEQFILT_EQ2BE 4
1977 #define FM_DACMBCEN_MBCEN2 0x2
1978 #define FV_MBCEN2_ENABLE 0x2
1993 #define FB_DACMBCCTL_WINSEL3 4
2003 #define FM_DACMBCCTL_LVLMODE1 0x2
2009 #define FB_DACCLECTL_LVLMODE 4
2021 #define FM_DACCLECTL_LIMEN 0x2
2022 #define FV_LIMEN_ENABLE 0x2
2107 #define FB_DACFXCTL_3DEN 4
2117 #define FM_DACFXCTL_BEEN 0x2
2128 #define FB_SUBEQFILT_EQ2BE 4
2181 #define FM_SUBMBCEN_MBCEN2 0x2
2182 #define FV_MBCEN2_ENABLE 0x2
2197 #define FB_SUBMBCCTL_WINSEL3 4
2207 #define FM_SUBMBCCTL_LVLMODE1 0x2
2213 #define FB_SUBCLECTL_LVLMODE 4
2225 #define FM_SUBCLECTL_LIMEN 0x2
2226 #define FV_LIMEN_ENABLE 0x2
2318 #define FM_SUBFXCTL_BEEN 0x2