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/freebsd/share/man/man4/
H A Diwlwifi.451 .Xr iwlwififw 4
63 .Xr iwm 4 ,
66 .Xr iwn 4
78 .Xr net80211 4
149 Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz
155 Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz
157 Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz
159 Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)
161 Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)
165 Intel(R) Wi-Fi 6 AX200 160MHz
[all …]
H A Dahc.489 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
91 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
92 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
93 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
94 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
95 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
96 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
97 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
98 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
99 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
[all …]
H A Dsym.4204 .Bl -column sym53c1510d "80MHz" "Width" "SRAM" "PCI64"
206 .It "sym53c810 10MHz 8Bit N N Y"
207 .It "sym53c810a 10MHz 8Bit N N Y"
208 .It "sym53c815 10MHz 8Bit N N Y"
209 .It "sym53c825 10MHz 16Bit N N Y"
210 .It "sym53c825a 10MHz 16Bit 4KB N Y"
211 .It "sym53c860 20MHz 8Bit N N Y"
212 .It "sym53c875 20MHz 16Bit 4KB N Y"
213 .It "sym53c876 20MHz 16Bit 4KB N Y"
214 .It "sym53c885 20MHz 16Bit 4KB N Y"
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
[all...]
H A Dmac.h13 #define MAC_INDEX_AUX 4
36 * @MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
46 #define MAC_FLG_SHORT_SLOT BIT(4)
90 NUM_TSF_IDS = 4,
142 * during 802.1X negotiation (and allowed during 4-way-HS)
149 BROADCAST_TWT_SUPPORTED = BIT(4),
244 MAC_FILTER_DIS_GRP_DECRYPT = BIT(4),
265 MAC_QOS_FLG_TXOP_TYPE = BIT(4),
279 * One instance of this config struct for each of 4 EDCA access categories
441 #define MAX_CHANNEL_BW_INDX_API_D_VER_1 4
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt24 "ohci-phy-4pin-dpdm",
28 "ohci-tll-4pin-dpdm",
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c29 if (elen < 4) { in ieee802_11_parse_vendor_specific()
59 switch (pos[4]) { in ieee802_11_parse_vendor_specific()
79 pos[4], (unsigned long) elen); in ieee802_11_parse_vendor_specific()
83 case 4: in ieee802_11_parse_vendor_specific()
140 elems->sae_pk = pos + 4; in ieee802_11_parse_vendor_specific()
141 elems->sae_pk_len = elen - 4; in ieee802_11_parse_vendor_specific()
159 if (elen > 4 && in ieee802_11_parse_vendor_specific()
160 (pos[4] == VENDOR_VHT_SUBTYPE || in ieee802_11_parse_vendor_specific()
161 pos[4] == VENDOR_VHT_SUBTYPE2)) { in ieee802_11_parse_vendor_specific()
1029 sta_info_len = *(pos + 4); in ieee802_11_parse_link_assoc_req()
[all …]
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
194 *sec_chan = *pri_chan + 4; in get_pri_sec_chan()
196 *sec_chan = *pri_chan - 4; in get_pri_sec_chan()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pri/sec mismatch with BSS " in check_40mhz_2g4()
373 "40 MHz Intolerant is set on channel %d in BSS " in check_40mhz_2g4()
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/freebsd/contrib/tcpdump/
H A Dprint-802_11.c51 #define IEEE802_11_HT_CONTROL_LEN 4
56 #define IEEE802_11_FCS_LEN 4
150 * The subtype field of a data frame is, in effect, composed of 4 flag
164 #define FC_SUBTYPE(fc) (((fc) >> 4) & 0xF)
241 #define E_CF 4
430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi37 atlas0_alert_4: atlas0-alert-4 {
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
70 cooling-device = <&cpu4 3 4>, <&cpu5 3 4>,
71 <&cpu6 3 4>, <&cpu7 3 4>;
74 /* Set maximum frequency as 1500MHz */
76 cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
77 <&cpu6 4 5>, <&cpu7 4 5>;
80 /* Set maximum frequency as 1400MHz */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
90 cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
91 <&cpu1 THERMAL_NO_LIMIT 4>,
92 <&cpu2 THERMAL_NO_LIMIT 4>,
93 <&cpu3 THERMAL_NO_LIMIT 4>;
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
[all …]
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
97 for (i = 0; i < 4; i++) { in verify_80mhz()
99 u8 adj_chan = center_chan - 6 + i * 4; in verify_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
168 u8 adj_chan = center_chan - 14 + i * 4; in verify_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
232 u8 adj_chan = center_chan - 30 + i * 4; in verify_320mhz()
259 if (bw == BW40MINUS || (bw == BW40 && (((channel - 1) / 4) % 2))) { in verify_channel()
262 res2 = allow_channel(mode, op_class, channel - 4, NULL); in verify_channel()
266 res2 = allow_channel(mode, op_class, channel + 4, NULL); in verify_channel()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
58 4 - Examples
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
58 4 - Examples
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/dev/usb/serial/
H A Dumcs.h31 #define UMCS7840_MAX_PORTS 4
64 #define MCS7840_DEV_REG_SP4 0x0c /* Options for UART 4, R/W */
65 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
76 * 4, R/W */
103 * configuration for Port 4,
108 * 4, R/W */
128 * 4, contains number of
131 * 4, contains number of
163 * 4, R/W */
166 * enable flag for Port 4, R/W */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt19 4 tsecm Security Engine
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt6 - max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages
15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
23 - 3: 4mV/us
24 - 4: 2mV/us
38 max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>;
H A Dmaxim,max8952.yaml26 minItems: 4
27 maxItems: 4
32 Array of 4 integer values defining DVS voltages in microvolts. All values
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
49 - 3: 4mV/us
50 - 4: 2mV/us
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
153 { 4, 3},
154 { 5, 4},
172 { 4, 3},
173 { 6, 4},
184 { 4, 3},
185 { 5, 4},
209 {4, 3},
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,dwc3.yaml76 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
77 60MHz for HS operation.
82 mode. Its frequency should be 19.2MHz.
183 - description: Master/Core clock, has to be >= 125 MHz
184 for SS operation and >= 60MHz for HS operation.
229 maxItems: 4
251 maxItems: 4
271 maxItems: 4
311 minItems: 4
409 maxItems: 4
[all...]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml50 description: Divides the device's core clock by a factor of 4.
60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
69 4: 89
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
93 4: Generic channel 0
112 description: Multiplies all touch and deep-touch thresholds by 4.
260 limited to 4 in the case of the ULP channel, and the property is un-
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
[all …]
H A Diqs269a.yaml61 description: Divides the device's core clock by a factor of 4.
180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (50
[all...]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
66 - const: 4
108 data-lanes = <1 2 3 4>;
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
86 0xc000 0 0 3 &media5200_fpga 0 4
87 0xc000 0 0 4 &media5200_fpga 0 5
90 0xc800 0 0 2 &media5200_fpga 0 4
92 0xc800 0 0 4 &media5200_fpga 0 2
94 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
113 bank-width = <4>; // Width in bytes of the flash bank
[all …]

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