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/linux/lib/zstd/compress/
H A D	clevels.h	1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause / 6 This source code is licensed under both the BSD-style license (found in the 9 * You may select, at your option, one of the above-listed licenses. 18 /-===== Pre-defined compression levels =====-/ 24 static const ZSTD_compressionParameters ZSTD_defaultCParameters[4][ZSTD_MAX_CLEVEL+1] = { 25 { /* "default" - for any srcSize > 256 KB / 28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, / level 1 / 29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, / level 2 / 30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, / level 3 / 31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, / level 4 */ [all …]
/linux/scripts/gdb/linux/
H A D	pgtable.py	`1 # SPDX-License-Identifier: GPL-2.0-only 18 def page_mask(level=1): argument 19 # 4KB 20 if level == 1: 23 elif level == 2: 26 elif level == 3: 29 raise Exception(f'Unknown page level 46 entry_va(level, phys_addr, translating_va) global() argument 47 start_bit(level) global() argument 89 __init__(self, address, level) global() argument 154 page_size_line(ps_bit, ps, level) global() argument [all...]`
/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A D	irqsrcs_dcn_1_0.h	30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 43 #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse [all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A D	hip07.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 compatible = "hisilicon,hip07-d05"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 17 compatible = "arm,psci-0.2"; 22 #address-cells = <1>; 23 #size-cells = <0>; 25 cpu-map { [all …]`
/linux/sound/soc/sof/xtensa/
H A D	core.c	1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 14 #include "../sof-priv.h" 23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa 33 {4, "Level1InterruptCause", 34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"}, 54 "An instruction fetch referenced a virtual address at a ring level less than CRING"}, 62 "A load or store referenced a virtual address at a ring level less than CRING"}, 74 "Coprocessor 4 instruction when cp4 disabled"}, 84 static void xtensa_dsp_oops(struct snd_sof_dev sdev, const char level, void *oops) in xtensa_dsp_oops() argument 89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n"); in xtensa_dsp_oops() [all …]
/linux/Documentation/devicetree/bindings/cache/
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache 33 maxItems: 4 [all …]
/linux/arch/arm64/boot/dts/rockchip/
H A D	rockchip-pinconf.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /omit-if-no-ref/ 8 pcfg_pull_up: pcfg-pull-up { 9 bias-pull-up; 12 /omit-if-no-ref/ 13 pcfg_pull_down: pcfg-pull-down { 14 bias-pull-down; 17 /omit-if-no-ref/ 18 pcfg_pull_none: pcfg-pull-none { 19 bias-disable; [all …]`
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a … [all …]
/linux/Documentation/admin-guide/pm/
H A D	intel-speed-select.rst	1 .. SPDX-License-Identifier: GPL-2.0 14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic… 15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha… 19 dynamically without pre-configuring via BIOS setup options. This dynamic 29 intel-speed-select configuration tool 32 Most Linux distribution packages may include the "intel-speed-select" tool. If not, 38 # cd tools/power/x86/intel-speed-select/ 43 ------------ 47 # intel-speed-select --help 49 The top-level help describes arguments and features. Notice that there is a [all …]
/linux/arch/sparc/kernel/
H A D	sun4m_irq.c	`1 // SPDX-License-Identifier: GPL-2.0 28 * 0x22 - Power 29 * 0x24 - ESP SCSI 30 * 0x26 - Lance ethernet 31 * 0x2b - Floppy 32 * 0x2c - Zilog uart 33 * 0x32 - SBUS level 0 34 * 0x33 - Parallel port, SBUS level 1 35 * 0x35 - SBUS level 2 36 * 0x37 - SBUS level 3 [all …]`
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …tion": "A directory write to the Level-1 Data Cache directory where the returned cache line was so… 10 "Unit": "CPU-M-CF", 14 …n": "A directory write to the Level-1 Instruction Cache directory where the returned cache line wa… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 31 "Unit": "CPU-M-CF", 35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache." [all …]
/linux/arch/arc/include/asm/
H A D	pgtable-levels.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 16 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS) 19 * ------------------------------------------------------- 20 * \| \| <---------- PGDIR_SHIFT ----------> \| 21 * \| \| \| <-- PAGE_SHIFT --> \| 22 * ------------------------------------------------------- 24 * \| \| --> off in page frame 25 * \| ---> index into Page Table 26 * ----> index into Page Directory 29 * However enabling of super page in a 2 level regime pegs PGDIR_SHIFT to [all …]
/linux/include/linux/
H A D	pxa2xx_ssp.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 5 This driver supports the following PXA CPU/SSP ports:- 50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] / 51 #define SSCR0_FRF GENMASK(5, 4) / FRame Format (mask) / 52 #define SSCR0_Motorola (0x0 << 4) / Motorola's Serial Peripheral Interface (SPI) / 53 #define SSCR0_TI (0x1 << 4) / Texas Instruments' Synchronous Serial Protocol (SSP) / 54 #define SSCR0_National (0x2 << 4) / National Microwire / 65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) / Time slots per frame [1..8] / 72 #define SSCR1_LBM BIT(2) / Loop-Back Mode / 74 #define SSCR1_SPH BIT(4) / Motorola SPI SSPSCLK phase setting */ [all …]
/linux/include/dt-bindings/pinctrl/
H A D	qcom,pmic-mpp.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 4 Multi-Purpose Pin binding. 10 /* power-source / 12 / Digital Input/Output: level [PM8058] / 18 / Digital Input/Output: level [PM8901] / 23 #define PM8901_MPP_VPH 4 25 / Digital Input/Output: level [PM8921] / 28 #define PM8921_MPP_L17 4 31 / Digital Input/Output: level [PM8821] / 35 / Digital Input/Output: level [PM8018] */ [all …]`
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	virtual-memory.json	3 … the number of page walks initiated by a demand load that missed the first and second level TLBs.", 4 "Counter": "0,1,2,3,4,5,6,7", 12 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 13 "Counter": "0,1,2,3,4,5,6,7", 22 "Counter": "0,1,2,3,4,5,6,7,8,9", 25 …licDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 32 "Counter": "0,1,2,3,4,5,6,7,8,9", 43 "Counter": "0,1,2,3,4,5,6,7", 53 "Counter": "0,1,2,3,4,5,6,7,8,9", 63 "Counter": "0,1,2,3,4,5,6,7,8,9", [all …]
/linux/Documentation/arch/s390/
H A D	s390dbf.rst	`6 - arch/s390/kernel/debug.c 7 - arch/s390/include/asm/debug.h 10 ------------ 24 ------- 31 which are written by event- and exception-calls. 33 An event-call writes the specified debug entry to the active debug 39 An exception-call writes the specified debug entry to the log and 48 There are four versions for the event- and exception-calls: One for 50 and one for sprintf-like formatted strings. 54 - Timestamp [all …]`
/linux/security/selinux/ss/
H A D	constraint.h	1 /* SPDX-License-Identifier: GPL-2.0 / 6 beyond the type-based rules in `te' or the role-based 28 #define CEXPR_ATTR 4 /* attr op attr / 34 #define CEXPR_TYPE 4 / type / 37 #define CEXPR_L1L2 32 / low level 1 vs. low level 2 / 38 #define CEXPR_L1H2 64 / low level 1 vs. high level 2 / 39 #define CEXPR_H1L2 128 / high level 1 vs. low level 2 / 40 #define CEXPR_H1H2 256 / high level 1 vs. high level 2 / 41 #define CEXPR_L1H1 512 / low level 1 vs. high level 1 / 42 #define CEXPR_L2H2 1024 / low level 2 vs. high level 2 */ [all …]
/linux/arch/arm64/include/asm/
H A D	kvm_arm.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 Copyright (C) 2012,2013 - ARM Ltd 153 * We configure the Stage-2 page tables to always restrict the IPA space to be 159 * Note that when using 4K pages, we concatenate two first level page tables 160 * together. With 16K pages, we concatenate 16 first level page tables. 168 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 172 * ----------------------------------------- 173 * \| Entry level \| 4K \| 16K/64K \| 174 * ------------------------------------------ 175 * \| Level: 0 \| 2 \| - \| [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	3 "Unit": "CPU-M-CF", 7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 17 "Unit": "CPU-M-CF", 21 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… 24 "Unit": "CPU-M-CF", 28 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 31 "Unit": "CPU-M-CF", 35 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… [all …]
/linux/Documentation/networking/
H A D	netif-msg.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 NETIF Msg Level 7 The design of the network interface message level setting. 10 ------- 18 integer variable that controls the debug message level. The message 19 level ranged from 0 to 7, and monotonically increased in verbosity. 21 The message level was not precisely defined past level 3, but were 22 always implemented within +-1 of the specified level. Drivers tended 23 to shed the more verbose level messages as they matured. 25 - 0 Minimal messages, only essential information on fatal errors. [all …]
/linux/drivers/soc/mediatek/
H A D	mtk-dvfsrc.c	1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/arm-smccc.h> 28 #define DVFSRC_V2_SW_REQ_VCORE_LEVEL GENMASK(6, 4) 76 void (set_opp_level)(struct mtk_dvfsrc dvfsrc, u32 level); 77 void (set_vcore_level)(struct mtk_dvfsrc dvfsrc, u32 level); 78 void (set_vscp_level)(struct mtk_dvfsrc dvfsrc, u32 level); 79 int (wait_for_opp_level)(struct mtk_dvfsrc dvfsrc, u32 level); 80 int (wait_for_vcore_level)(struct mtk_dvfsrc dvfsrc, u32 level); 86 return readl(dvfs->regs + dvfs->dvd->regs[offset]); in dvfsrc_readl() 91 writel(val, dvfs->regs + dvfs->dvd->regs[offset]); in dvfsrc_writel() [all …]
/linux/tools/testing/selftests/net/forwarding/
H A D	tc_flower_cfm.sh	2 # SPDX-License-Identifier: GPL-2.0 46 )"$(u8_to_hex $((mdl << 5))):"$( : MD level and Version 66 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 67 pkt="$ethtype $(generate_cfm_hdr 6 5 0 4)" 68 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 77 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 104 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 106 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 108 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac "$pkt" -q 111 check_err $? "Did not match on correct level" [all …]
/linux/Documentation/arch/x86/
H A D	topology.rst	`1 .. SPDX-License-Identifier: GPL-2.0 11 The architecture-agnostic topology definitions are in 12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific 17 Needless to say, code should use the generic functions - this file is only 35 - packages 36 - cores 37 - threads 48 Package-related topology information in the kernel: 50 - topology_num_threads_per_package() 54 - topology_num_cores_per_package() [all …]`
/linux/arch/arm64/boot/dts/realtek/
H A D	rtd16xx.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 13 interrupt-parent = <&gic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 17 reserved-memory { 18 #address-cells = <1>; 19 #size-cells = <1>; 32 no-map; [all …]`
/linux/Documentation/arch/powerpc/
H A D	vmemmap_dedup.rst	1 .. SPDX-License-Identifier: GPL-2.0 7 The device-dax interface uses the tail deduplication technique explained in 14 With 2M PMD level mapping, we require 32 struct pages and a single 64K vmemmap 18 With 1G PUD level mapping, we require 16384 struct pages and a single 64K 20 require 16 64K pages in vmemmap to map the struct page for 1G PUD level mapping. 22 Here's how things look like on device-dax after the sections are populated:: 23 +-----------+ ---virt_to_page---> +-----------+ mapping to +-----------+ 24 \| \| \| 0 \| -------------> \| 0 \| 25 \| \| +-----------+ +-----------+ 26 \| \| \| 1 \| -------------> \| 1 \| [all …]

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