Lines Matching +full:4 +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
153 * We configure the Stage-2 page tables to always restrict the IPA space to be
159 * Note that when using 4K pages, we concatenate two first level page tables
160 * together. With 16K pages, we concatenate 16 first level page tables.
168 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
172 * -----------------------------------------
173 * | Entry level | 4K | 16K/64K |
174 * ------------------------------------------
175 * | Level: 0 | 2 | - |
176 * ------------------------------------------
177 * | Level: 1 | 1 | 2 |
178 * ------------------------------------------
179 * | Level: 2 | 0 | 1 |
180 * ------------------------------------------
181 * | Level: 3 | - | 0 |
182 * ------------------------------------------
186 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
189 * TGRAN_SL0_BASE(4K) = 2
193 * Entry_Level = 4 - Number_of_levels.
206 #else /* 4K */
214 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
216 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
221 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
224 * ARM VMSAv8-64 defines an algorithm for finding the translation table
228 * addresses for each level, based on PAGE_SIZE, entry level
231 * level and thus determines the alignment of VTTBR:BADDR for stage2
232 * page table entry level.
233 * Since the number of bits resolved at the entry level could vary
235 * Magic constant for a given PAGE_SIZE and Entry Level. The
239 * The value of "x" for entry level is calculated as :
240 * x = Magic_N - T0SZ
243 * level of the page table as below:
245 * --------------------------------------------
246 * | Entry level | 4K 16K 64K |
247 * --------------------------------------------
248 * | Level: 0 (4 levels) | 28 | - | - |
249 * --------------------------------------------
250 * | Level: 1 (3 levels) | 37 | 31 | 25 |
251 * --------------------------------------------
252 * | Level: 2 (2 levels) | 46 | 42 | 38 |
253 * --------------------------------------------
254 * | Level: 3 (1 level) | - | 53 | 51 |
255 * --------------------------------------------
259 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
261 * where Number_of_levels = (4 - Level). We are only interested in the
264 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
266 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
267 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
273 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
276 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
277 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
281 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
286 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
290 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
336 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
337 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
344 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
367 { PSR_AA32_MODE_USR, "32-bit USR" }, \
368 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \
369 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \
370 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \
371 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \
372 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \
373 { PSR_AA32_MODE_UND, "32-bit UND" }, \
374 { PSR_AA32_MODE_SYS, "32-bit SYS" }