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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
11 #define _VLV_CMN(dw) (0x8100 + (dw) * 4)
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
14 #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
16 #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
17 #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
18 #define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
[all …]
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
93 int lane; in intel_cx0_program_msgbus_timer() local
95 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) in intel_cx0_program_msgbus_timer()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
134 int lane) in intel_clear_response_ready_flag() argument
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H A Dbxt_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
21 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
24 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
25 (reg_ch1) - _BXT_PHY0_BASE))
28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
99 (idx) * 4)
101 /* BXT PHY common lane registers */
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
77 #define PLL_READY_TX_BIT BIT(4)
110 #define CLK100M_125M_EN BIT(4)
130 #define PRD_TXSWING_MASK BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
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H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
57 { 4, 5, 0 },
58 { 0, 4, 0 },
59 { 0, 0, 4 },
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
69 if (priv->conf) { in a38x_set_conf()
70 conf = readl_relaxed(priv->conf); in a38x_set_conf()
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/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
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H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
101 #define HSIC_PD_RX_DATA0 BIT(4)
123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
134 #define HSIC_CAP_CFG BIT(4)
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
47 #define HSIO_IOB_A_0_M1M0_2 BIT(4)
48 #define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
53 #define HSIO_LANE0_TX_PLL_LOCK BIT(4)
57 #define HSIO_LTSSM_ENABLE BIT(4)
96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
113 .reg_stride = 4,
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
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/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
4 // tegra186_asrc.c - Tegra186 ASRC driver
30 (((id) + 1) << 4) }, \
47 ASRC_STREAM_REG_DEFAULTS(4),
72 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
82 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
83 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
93 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
100 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
30 * Lane Registers
33 /* TX De-emphasis parameters */
49 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
83 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
96 #define L3_NSW_PIPE_SHIFT 4
106 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
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/linux/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
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H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
34 * lane 0, used for the transmissions on main link.
36 * Allowed values: 1, 2, 4
44 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
49 unsigned int voltage[4];
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value per lane.
59 unsigned int pre[4];
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
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/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
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/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
129 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
130 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
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/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 switch (dp->link.cap.link_rate) { in hibmc_dp_get_serdes_rate_cfg()
24 return -EINVAL; in hibmc_dp_get_serdes_rate_cfg()
33 /* DP 2 lane */ in hibmc_dp_link_training_configure()
35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
42 /* set rate and lane count */ in hibmc_dp_link_training_configure()
43 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
45 ret = drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); in hibmc_dp_link_training_configure()
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/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
25 * [30] clock lane soft reset.
26 * [29] data byte lane 3 soft reset.
27 * [28] data byte lane 2 soft reset.
28 * [27] data byte lane 1 soft reset.
29 * [26] data byte lane 0 soft reset.
37 * 1: /4. 0: /2.
43 * [4] HS data endian.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-io.json13 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
14 "ScaleUnit": "4Bytes",
29 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
30 "ScaleUnit": "4Bytes",
44 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
147 "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
205 …ouble word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged …
218 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
231 …on": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; …
244 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
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/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-io.json13 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
14 "ScaleUnit": "4Bytes",
29 …4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general cas…
30 "ScaleUnit": "4Bytes",
44 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
147 "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
205 …ouble word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged …
218 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
231 …on": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; …
244 …"PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the at…
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
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/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Duncore-io.json34 "Counter": "4",
102 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
110 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
123 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
136 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
149 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
162 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
167 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
175 … : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is …
188 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-io.json34 "Counter": "4",
182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
203 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
216 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
229 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
242 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
247 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
255 … : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is …
268 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]

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