Lines Matching +full:4 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
129 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
130 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
132 *pins = &pinctrl->desc->pins[group].number; in tegra_xusb_padctl_get_group_pins()
168 if (err != -EINVAL) in tegra_xusb_padctl_parse_subnode()
177 if (err == -EINVAL) in tegra_xusb_padctl_parse_subnode()
185 err = pinctrl_utils_add_config(padctl->pinctrl, &configs, in tegra_xusb_padctl_parse_subnode()
203 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps, in tegra_xusb_padctl_parse_subnode()
210 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps, in tegra_xusb_padctl_parse_subnode()
218 err = pinctrl_utils_add_map_configs(padctl->pinctrl, in tegra_xusb_padctl_parse_subnode()
269 return padctl->soc->num_functions; in tegra_xusb_padctl_get_functions_count()
278 return padctl->soc->functions[function].name; in tegra_xusb_padctl_get_function_name()
288 *num_groups = padctl->soc->functions[function].num_groups; in tegra_xusb_padctl_get_function_groups()
289 *groups = padctl->soc->functions[function].groups; in tegra_xusb_padctl_get_function_groups()
299 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
303 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
305 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_pinmux_set()
306 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
309 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
310 return -EINVAL; in tegra_xusb_padctl_pinmux_set()
312 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
313 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
314 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
315 padctl_writel(padctl, value, lane->offset); in tegra_xusb_padctl_pinmux_set()
332 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_get() local
337 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
342 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_get()
343 return -EINVAL; in tegra_xusb_padctl_pinconf_group_get()
345 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinconf_group_get()
347 if (value & BIT(lane->iddq)) in tegra_xusb_padctl_pinconf_group_get()
356 dev_err(padctl->dev, "invalid configuration parameter: %04x\n", in tegra_xusb_padctl_pinconf_group_get()
358 return -ENOTSUPP; in tegra_xusb_padctl_pinconf_group_get()
370 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_set() local
376 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_set()
385 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_set()
386 return -EINVAL; in tegra_xusb_padctl_pinconf_group_set()
388 regval = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinconf_group_set()
391 regval &= ~BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
393 regval |= BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
395 padctl_writel(padctl, regval, lane->offset); in tegra_xusb_padctl_pinconf_group_set()
399 dev_err(padctl->dev, in tegra_xusb_padctl_pinconf_group_set()
402 return -ENOTSUPP; in tegra_xusb_padctl_pinconf_group_set()
481 mutex_lock(&padctl->lock); in tegra_xusb_padctl_enable()
483 if (padctl->enable++ > 0) in tegra_xusb_padctl_enable()
503 mutex_unlock(&padctl->lock); in tegra_xusb_padctl_enable()
511 mutex_lock(&padctl->lock); in tegra_xusb_padctl_disable()
513 if (WARN_ON(padctl->enable == 0)) in tegra_xusb_padctl_disable()
516 if (--padctl->enable > 0) in tegra_xusb_padctl_disable()
536 mutex_unlock(&padctl->lock); in tegra_xusb_padctl_disable()
558 int err = -ETIMEDOUT; in pcie_phy_power_on()
614 int err = -ETIMEDOUT; in sata_phy_power_on()
688 unsigned int index = args->args[0]; in tegra_xusb_padctl_xlate()
690 if (args->args_count <= 0) in tegra_xusb_padctl_xlate()
691 return ERR_PTR(-EINVAL); in tegra_xusb_padctl_xlate()
693 if (index >= ARRAY_SIZE(padctl->phys)) in tegra_xusb_padctl_xlate()
694 return ERR_PTR(-EINVAL); in tegra_xusb_padctl_xlate()
696 return padctl->phys[index]; in tegra_xusb_padctl_xlate()
703 #define PIN_HSIC_0 4
713 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
714 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
715 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
716 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
717 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
718 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
719 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
720 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
721 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
722 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
723 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
724 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
728 "otg-0",
729 "otg-1",
730 "otg-2",
731 "ulpi-0",
732 "hsic-0",
733 "hsic-1",
737 "otg-0",
738 "otg-1",
739 "otg-2",
740 "ulpi-0",
741 "hsic-0",
742 "hsic-1",
746 "otg-0",
747 "otg-1",
748 "otg-2",
752 "pcie-0",
753 "pcie-1",
754 "pcie-2",
755 "pcie-3",
756 "pcie-4",
760 "pcie-0",
761 "pcie-1",
762 "sata-0",
766 "sata-0",
770 "otg-0",
771 "otg-1",
772 "otg-2",
773 "pcie-0",
774 "pcie-1",
775 "pcie-2",
776 "pcie-3",
777 "pcie-4",
778 "sata-0",
839 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
840 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
841 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
842 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
843 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
844 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
845 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
846 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
847 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
848 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
849 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
850 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
863 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
879 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL); in tegra_xusb_padctl_legacy_probe()
881 return -ENOMEM; in tegra_xusb_padctl_legacy_probe()
884 mutex_init(&padctl->lock); in tegra_xusb_padctl_legacy_probe()
885 padctl->dev = &pdev->dev; in tegra_xusb_padctl_legacy_probe()
893 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); in tegra_xusb_padctl_legacy_probe()
894 padctl->soc = match->data; in tegra_xusb_padctl_legacy_probe()
896 padctl->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_xusb_padctl_legacy_probe()
897 if (IS_ERR(padctl->regs)) in tegra_xusb_padctl_legacy_probe()
898 return PTR_ERR(padctl->regs); in tegra_xusb_padctl_legacy_probe()
900 padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in tegra_xusb_padctl_legacy_probe()
901 if (IS_ERR(padctl->rst)) in tegra_xusb_padctl_legacy_probe()
902 return PTR_ERR(padctl->rst); in tegra_xusb_padctl_legacy_probe()
904 err = reset_control_deassert(padctl->rst); in tegra_xusb_padctl_legacy_probe()
908 memset(&padctl->desc, 0, sizeof(padctl->desc)); in tegra_xusb_padctl_legacy_probe()
909 padctl->desc.name = dev_name(padctl->dev); in tegra_xusb_padctl_legacy_probe()
910 padctl->desc.pins = tegra124_pins; in tegra_xusb_padctl_legacy_probe()
911 padctl->desc.npins = ARRAY_SIZE(tegra124_pins); in tegra_xusb_padctl_legacy_probe()
912 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; in tegra_xusb_padctl_legacy_probe()
913 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; in tegra_xusb_padctl_legacy_probe()
914 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; in tegra_xusb_padctl_legacy_probe()
915 padctl->desc.owner = THIS_MODULE; in tegra_xusb_padctl_legacy_probe()
917 padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc, in tegra_xusb_padctl_legacy_probe()
919 if (IS_ERR(padctl->pinctrl)) { in tegra_xusb_padctl_legacy_probe()
920 dev_err(&pdev->dev, "failed to register pincontrol\n"); in tegra_xusb_padctl_legacy_probe()
921 err = PTR_ERR(padctl->pinctrl); in tegra_xusb_padctl_legacy_probe()
925 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops); in tegra_xusb_padctl_legacy_probe()
931 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; in tegra_xusb_padctl_legacy_probe()
934 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops); in tegra_xusb_padctl_legacy_probe()
940 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy; in tegra_xusb_padctl_legacy_probe()
943 padctl->provider = devm_of_phy_provider_register(&pdev->dev, in tegra_xusb_padctl_legacy_probe()
945 if (IS_ERR(padctl->provider)) { in tegra_xusb_padctl_legacy_probe()
946 err = PTR_ERR(padctl->provider); in tegra_xusb_padctl_legacy_probe()
947 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); in tegra_xusb_padctl_legacy_probe()
954 reset_control_assert(padctl->rst); in tegra_xusb_padctl_legacy_probe()
964 err = reset_control_assert(padctl->rst); in tegra_xusb_padctl_legacy_remove()
966 dev_err(&pdev->dev, "failed to assert reset: %d\n", err); in tegra_xusb_padctl_legacy_remove()