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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/linux/Documentation/translations/zh_CN/core-api/
H A Dcpu_hotplug.rst1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cpu_hotplug.rst
79 hot-add/hot-remove。目前还没有定死规定。典型的用法是在启动时启动拓扑结构，这时
95 $ ls -lh /sys/devices/system/cpu
97 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
98 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
99 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
100 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
101 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
102 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
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H A Dworkqueue.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/core-api/workqueue.rst
109 每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当
139 参数 - ``@name`` , ``@flags`` 和 ``@max_active`` 。
148 ---------
202 --------------
234 0 w0 starts and burns CPU
236 15 w0 wakes up and burns CPU
238 20 w1 starts and burns CPU
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/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/linux/Documentation/core-api/
H A Dcpu_hotplug.rst2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
53 CPU maps
66 after a CPU is available for kernel scheduling and ready to receive
67 interrupts from devices. Its cleared when a CPU is brought down using
69 migrated to another target CPU.
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/linux/arch/arm64/boot/dts/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
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/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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/linux/arch/arm64/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
27 * may prevent a CPU from being onlined at all.
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
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/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@900 {
22 compatible = "arm,cortex-a9";
[all …]
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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/linux/include/linux/irqchip/
H A Dirq-bcm2836.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
33 * The CPU's interrupt status register. Bits are defined by the
[all …]
/linux/Documentation/admin-guide/
H A Dcputopology.rst2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
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/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/cpu.h>
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
49 * Thread | 0 1 2 3 4 5 6 7 |
50 * ----------------------------
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/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
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/linux/arch/x86/
H A DKconfig.cpu1 # SPDX-License-Identifier: GPL-2.0
2 # Put here option for CPU selection and depending optimization
4 prompt "x86-32 Processor family"
8 This is the processor type of your CPU. This information is
10 that can run on all supported x86 CPU types (albeit not
15 UMC 486SX-S and the NexGen Nx586.
22 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
24 - "586" for generic Pentium CPUs lacking the TSC
26 - "Pentium-Classic" for the Intel Pentium.
27 - "Pentium-MMX" for the Intel Pentium MMX.
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/linux/drivers/irqchip/
H A Dirq-gic.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * o There is one CPU Interface per CPU, which sends interrupts sent
12 * associated CPU. The base address of the CPU interface is usually
14 * on the CPU it is accessed from.
16 * Note that IRQs 0-31 are special - they are local to each CPU.
18 * registers are banked per-cpu for these sources.
27 #include <linux/cpu.h>
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
80 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Duncore-io.json34 "Counter": "4",
102 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
110 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
167 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
175 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
282 "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4",
334 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0-7",
346 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
353 …"PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of …
358 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
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/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-io.json34 "Counter": "4",
182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
247 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
255 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
362 "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4",
414 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0-7",
426 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
433 …"PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of …
438 "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
[all …]
/linux/drivers/clk/mvebu/
H A Dkirkwood.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
15 #include <linux/clk-provider.h>
24 * Kirkwood PLL sample-at-reset configuration
27 * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
28 * 4 = 600 MHz
38 * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
39 * 1 = (1/2) * CPU
40 * 3 = (1/3) * CPU
41 * 5 = (1/4) * CPU
[all …]
/linux/arch/loongarch/kvm/intc/
H A Deiointc.c1 // SPDX-License-Identifier: GPL-2.0
12 int ipnum, cpu, cpuid, irq; in eiointc_set_sw_coreisr() local
16 ipnum = s->ipmap.reg_u8[irq / 32]; in eiointc_set_sw_coreisr()
17 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
19 ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0; in eiointc_set_sw_coreisr()
22 cpuid = s->coremap.reg_u8[irq]; in eiointc_set_sw_coreisr()
23 vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid); in eiointc_set_sw_coreisr()
27 cpu = vcpu->vcpu_id; in eiointc_set_sw_coreisr()
28 if (test_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu])) in eiointc_set_sw_coreisr()
29 __set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Defines x86 CPU feature bits
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
25 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
46 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
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/linux/Documentation/tools/rtla/
H A Drtla-hwnoise.rst1 .. SPDX-License-Identifier: GPL-2.0
6 rtla-hwnoise
8 ------------------------------------------
9 Detect and quantify hardware-related noise
10 ------------------------------------------
24 of threads as a consequence, only non-maskable interrupts and hardware-related
40 In the example below, the **rtla hwnoise** tool is set to run on CPUs *1-7*
41 on a system with 8 cores/16 threads with hyper-threading enabled.
47 # rtla hwnoise -c 1-7 -T 1 -d 10m -q
48 Hardware-related Noise
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/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Defines x86 CPU feature bits
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
25 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
46 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
[all …]

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