Lines Matching +full:4 +full:- +full:cpu
15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
36 model = "PowerPC,4xx"; // real CPU changed in sim
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
44 dcr-controller;
45 dcr-access-method = "native";
48 cpu@1 {
49 device_type = "cpu";
50 model = "PowerPC,4xx"; // real CPU changed in sim
52 clock-frequency = <100000000>; // 100Mhz :-)
53 timebase-frequency = <100000000>;
54 i-cache-line-size = <32>;
55 d-cache-line-size = <32>;
56 i-cache-size = <32768>;
57 d-cache-size = <32768>;
58 dcr-controller;
59 dcr-access-method = "native";
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0x01f00100>;
64 cpu@2 {
65 device_type = "cpu";
66 model = "PowerPC,4xx"; // real CPU changed in sim
68 clock-frequency = <100000000>; // 100Mhz :-)
69 timebase-frequency = <100000000>;
70 i-cache-line-size = <32>;
71 d-cache-line-size = <32>;
72 i-cache-size = <32768>;
73 d-cache-size = <32768>;
74 dcr-controller;
75 dcr-access-method = "native";
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0x01f00200>;
80 cpu@3 {
81 device_type = "cpu";
82 model = "PowerPC,4xx"; // real CPU changed in sim
84 clock-frequency = <100000000>; // 100Mhz :-)
85 timebase-frequency = <100000000>;
86 i-cache-line-size = <32>;
87 d-cache-line-size = <32>;
88 i-cache-size = <32768>;
89 d-cache-size = <32768>;
90 dcr-controller;
91 dcr-access-method = "native";
93 enable-method = "spin-table";
94 cpu-release-addr = <0 0x01f00300>;
104 MPIC: interrupt-controller {
105 compatible = "chrp,open-pic";
106 interrupt-controller;
107 dcr-reg = <0xffc00000 0x00030000>;
108 #address-cells = <0>;
109 #size-cells = <0>;
110 #interrupt-cells = <2>;
115 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
116 #address-cells = <2>;
117 #size-cells = <1>;
119 clock-frequency = <0>; // Filled in by zImage
122 compatible = "ibm,opb-4xx", "ibm,opb";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 /* Wish there was a nicer way of specifying a full 32-bit
129 clock-frequency = <0>; // Filled in by zImage
134 virtual-reg = <0xe0000200>;
135 clock-frequency = <11059200>;
136 current-speed = <115200>;
137 interrupt-parent = <&MPIC>;
144 compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
147 iss-block {
148 compatible = "ibm,iss-sim-block-device";
153 stdout-path = "/plb/opb/serial@40000200";