Lines Matching +full:4 +full:- +full:cpu

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 	#address-cells = <1>;
15 	#size-cells = <1>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
21 		cpu@900 {
22 			compatible = "arm,cortex-a9";
23 			device_type = "cpu";
25 			next-level-cache = <&L2>;
27 			clock-names = "cpu";
28 			operating-points = <
37 			clock-latency = <100000>;
40 		cpu@901 {
41 			compatible = "arm,cortex-a9";
42 			device_type = "cpu";
44 			next-level-cache = <&L2>;
46 			clock-names = "cpu";
47 			operating-points = <
56 			clock-latency = <100000>;
59 		cpu@902 {
60 			compatible = "arm,cortex-a9";
61 			device_type = "cpu";
63 			next-level-cache = <&L2>;
65 			clock-names = "cpu";
66 			operating-points = <
75 			clock-latency = <100000>;
78 		cpu@903 {
79 			compatible = "arm,cortex-a9";
80 			device_type = "cpu";
82 			next-level-cache = <&L2>;
84 			clock-names = "cpu";
85 			operating-points = <
94 			clock-latency = <100000>;
107 		memory-controller@fff00000 {
108 			compatible = "calxeda,hb-ddr-ctrl";
110 			interrupts = <0 91 4>;
114 			compatible = "arm,cortex-a9-twd-timer";
121 			compatible = "arm,cortex-a9-twd-wdt";
127 		intc: interrupt-controller@fff11000 {
128 			compatible = "arm,cortex-a9-gic";
129 			#interrupt-cells = <3>;
130 			interrupt-controller;
135 		L2: cache-controller {
136 			compatible = "arm,pl310-cache";
138 			interrupts = <0 70 4>;
139 			cache-unified;
140 			cache-level = <2>;
144 			compatible = "arm,cortex-a9-pmu";
145 			interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
150 			compatible = "calxeda,hb-sregs-l2-ecc";
152 			interrupts = <0 71 4>, <0 72 4>;
158 /include/ "ecx-common.dtsi"