Lines Matching +full:4 +full:- +full:cpu
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Defines x86 CPU feature bits
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
25 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
46 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
61 #define X86_FEATURE_LM ( 1*32+29) /* "lm" Long Mode (x86-64, 64-bit support) */
65 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
66 #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* "recovery" CPU in recovery mode */
70 /* Other features, Linux-defined mapping, word 3 */
76 #define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
77 #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
78 #define X86_FEATURE_ZEN6 ( 3*32+ 6) /* CPU based on Zen6 microarchitecture */
84 #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */
90 #define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* Clear CPU buffers using VERW */
93 #define X86_FEATURE_ALWAYS ( 3*32+21) /* Always-present feature */
94 #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* "xtopology" CPU topology enum extensions */
97 #define X86_FEATURE_CPUID ( 3*32+25) /* "cpuid" CPU has CPUID instruction itself */
99 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* "amd_dcm" AMD multi-node processor */
100 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* "aperfmperf" P-State hardware coordination feedback c…
105 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
106 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
107 #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* "pclmulqdq" PCLMULQDQ instruction */
108 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* "dtes64" 64-bit Debug Store */
109 #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */
110 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
111 #define X86_FEATURE_VMX ( 4*32+ 5) /* "vmx" Hardware virtualization */
112 #define X86_FEATURE_SMX ( 4*32+ 6) /* "smx" Safer Mode eXtensions */
113 #define X86_FEATURE_EST ( 4*32+ 7) /* "est" Enhanced SpeedStep */
114 #define X86_FEATURE_TM2 ( 4*32+ 8) /* "tm2" Thermal Monitor 2 */
115 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* "ssse3" Supplemental SSE-3 */
116 #define X86_FEATURE_CID ( 4*32+10) /* "cid" Context ID */
117 #define X86_FEATURE_SDBG ( 4*32+11) /* "sdbg" Silicon Debug */
118 #define X86_FEATURE_FMA ( 4*32+12) /* "fma" Fused multiply-add */
119 #define X86_FEATURE_CX16 ( 4*32+13) /* "cx16" CMPXCHG16B instruction */
120 #define X86_FEATURE_XTPR ( 4*32+14) /* "xtpr" Send Task Priority Messages */
121 #define X86_FEATURE_PDCM ( 4*32+15) /* "pdcm" Perf/Debug Capabilities MSR */
122 #define X86_FEATURE_PCID ( 4*32+17) /* "pcid" Process Context Identifiers */
123 #define X86_FEATURE_DCA ( 4*32+18) /* "dca" Direct Cache Access */
124 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
125 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
126 #define X86_FEATURE_X2APIC ( 4*32+21) /* "x2apic" X2APIC */
127 #define X86_FEATURE_MOVBE ( 4*32+22) /* "movbe" MOVBE instruction */
128 #define X86_FEATURE_POPCNT ( 4*32+23) /* "popcnt" POPCNT instruction */
129 #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* "tsc_deadline_timer" TSC deadline timer */
130 #define X86_FEATURE_AES ( 4*32+25) /* "aes" AES instructions */
131 #define X86_FEATURE_XSAVE ( 4*32+26) /* "xsave" XSAVE/XRSTOR/XSETBV/XGETBV instructions */
132 #define X86_FEATURE_OSXSAVE ( 4*32+27) /* XSAVE instruction enabled in the OS */
133 #define X86_FEATURE_AVX ( 4*32+28) /* "avx" Advanced Vector Extensions */
134 #define X86_FEATURE_F16C ( 4*32+29) /* "f16c" 16-bit FP conversions */
135 #define X86_FEATURE_RDRAND ( 4*32+30) /* "rdrand" RDRAND instruction */
136 #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* "hypervisor" Running on a hypervisor */
138 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
141 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
142 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
155 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* "cr8_legacy" CR8 in 32-bit mode */
157 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* "sse4a" SSE-4A */
166 #define X86_FEATURE_FMA4 ( 6*32+16) /* "fma4" 4 operands MAC instructions */
174 #define X86_FEATURE_PTSC ( 6*32+27) /* "ptsc" Performance time-stamp counter */
179 * Auxiliary flags: Linux defined - For features scattered in various
188 #define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* "cat_l3" Cache Allocation Technology L3 */
192 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* "hw_pstate" AMD HW-PState */
197 #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* Fill RSB on VM-Exit */
221 #define X86_FEATURE_COHERENCY_SFW_NO ( 8*32+ 4) /* SNP cache coherency software work around not nee…
225 #define X86_FEATURE_EPT_AD ( 8*32+17) /* "ept_ad" Intel Extended Page Table access-dirty bit */
232 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
237 #define X86_FEATURE_HLE ( 9*32+ 4) /* "hle" Hardware Lock Elision */
249 #define X86_FEATURE_AVX512F ( 9*32+16) /* "avx512f" AVX-512 Foundation */
250 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* "avx512dq" AVX-512 DQ (Double/Quad granular) Instructio…
254 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* "avx512ifma" AVX-512 Integer Fused Multiply-Add instr…
258 #define X86_FEATURE_AVX512PF ( 9*32+26) /* "avx512pf" AVX-512 Prefetch */
259 #define X86_FEATURE_AVX512ER ( 9*32+27) /* "avx512er" AVX-512 Exponential and Reciprocal */
260 #define X86_FEATURE_AVX512CD ( 9*32+28) /* "avx512cd" AVX-512 Conflict Detection */
262 #define X86_FEATURE_AVX512BW ( 9*32+30) /* "avx512bw" AVX-512 BW (Byte/Word granular) Instructions…
263 #define X86_FEATURE_AVX512VL ( 9*32+31) /* "avx512vl" AVX-512 VL (128/256 Vector Length) Extension…
270 #define X86_FEATURE_XFD (10*32+ 4) /* eXtended Feature Disabling */
273 * Extended auxiliary flags: Linux defined - for features scattered in various
282 #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* LFENCE in user entry SWAPGS path */
285 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
306 #define X86_FEATURE_ZEN2 (11*32+28) /* CPU based on Zen2 microarchitecture */
307 #define X86_FEATURE_ZEN3 (11*32+29) /* CPU based on Zen3 microarchitecture */
308 #define X86_FEATURE_ZEN4 (11*32+30) /* CPU based on Zen4 microarchitecture */
309 #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */
311 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
315 #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
319 #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
324 #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
329 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
334 #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
339 …E_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
355 #define X86_FEATURE_PLN (14*32+ 4) /* "pln" Intel Power Limit Notification */
357 #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
370 #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
372 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* "flushbyasid" Flush-by-ASID support */
386 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
390 #define X86_FEATURE_OSPKE (16*32+ 4) /* "ospke" OS Protection Keys Enable */
396 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* "vpclmulqdq" Carry-Less Multiplication Double Quadwor…
398 …512_BITALG (16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
401 #define X86_FEATURE_LA57 (16*32+16) /* "la57" 5-level page tables */
410 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
415 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
416 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* "avx512_4vnniw" AVX-512 Neural Network Instructions…
417 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* "avx512_4fmaps" AVX-512 Multiply Accumulation Singl…
418 #define X86_FEATURE_FSRM (18*32+ 4) /* "fsrm" Fast Short Rep Mov */
419 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* "avx512_vp2intersect" AVX-512 Intersect for D…
421 #define X86_FEATURE_MD_CLEAR (18*32+10) /* "md_clear" VERW clears CPU buffers */
441 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
445 #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted Stat…
446 #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Neste…
447 #define X86_FEATURE_SNP_SECURE_TSC (19*32+ 8) /* SEV-SNP Secure TSC */
449 #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
450 #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
455 #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages …
457 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
459 #define X86_FEATURE_WRMSR_XX_BASE_NS (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializi…
472 #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */
473 #define X86_FEATURE_SRSO_USER_KERNEL_NO (20*32+30) /* CPU is not affected by SRSO across user/kerne…
480 * Extended auxiliary flags: Linux defined - for features scattered in various
489 #define X86_FEATURE_CLEAR_BHB_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
496 #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
497 #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
498 #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using VERW before VMRUN */
499 #define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug …
512 #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
519 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
522 #define X86_BUG_ESPFIX X86_BUG(9) /* IRET to 16-bit SS corrupts ESP/RSP high bits */
526 #define X86_BUG_MONITOR X86_BUG(12) /* "monitor" IPI required to wake up remote CPU */
527 #define X86_BUG_AMD_E400 X86_BUG(13) /* "amd_e400" CPU is among the affected by Erratum 400 */
528 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* "cpu_meltdown" CPU is affected by meltdown attack and …
529 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* "spectre_v1" CPU is affected by Spectre variant 1 attack…
530 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* "spectre_v2" CPU is affected by Spectre variant 2 attack…
531 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* "spec_store_bypass" CPU is affected by speculative…
532 #define X86_BUG_L1TF X86_BUG(18) /* "l1tf" CPU is affected by L1 Terminal Fault */
533 #define X86_BUG_MDS X86_BUG(19) /* "mds" CPU is affected by Microarchitectural data sampling */
534 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* "msbds_only" CPU is only affected by the MSDBS variant …
535 #define X86_BUG_SWAPGS X86_BUG(21) /* "swapgs" CPU is affected by speculation through SWAPGS */
536 #define X86_BUG_TAA X86_BUG(22) /* "taa" CPU is affected by TSX Async Abort(TAA) */
537 #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* "itlb_multihit" CPU may incur MCE during certain page…
538 #define X86_BUG_SRBDS X86_BUG(24) /* "srbds" CPU may leak RNG bits if not mitigated */
539 #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* "mmio_stale_data" CPU is affected by Processor MMIO…
540 /* unused, was #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) "mmio_unknown" CPU is too old and its MMIO…
541 #define X86_BUG_RETBLEED X86_BUG(27) /* "retbleed" CPU is affected by RETBleed */
543 #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address…
544 #define X86_BUG_GDS X86_BUG(30) /* "gds" CPU is affected by Gather Data Sampling */
545 #define X86_BUG_TDX_PW_MCE X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does p…
550 #define X86_BUG_RFDS X86_BUG( 1*32+ 2) /* "rfds" CPU is vulnerable to Register File Data Sampling…
551 #define X86_BUG_BHI X86_BUG( 1*32+ 3) /* "bhi" CPU is affected by Branch History Injection */
552 #define X86_BUG_IBPB_NO_RET X86_BUG( 1*32+ 4) /* "ibpb_no_ret" IBPB omits return target prediction…
553 #define X86_BUG_SPECTRE_V2_USER X86_BUG( 1*32+ 5) /* "spectre_v2_user" CPU is affected by Spectre …
554 #define X86_BUG_OLD_MICROCODE X86_BUG( 1*32+ 6) /* "old_microcode" CPU has old microcode, it is su…
555 #define X86_BUG_ITS X86_BUG( 1*32+ 7) /* "its" CPU is affected by Indirect Target Selection */
556 #define X86_BUG_ITS_NATIVE_ONLY X86_BUG( 1*32+ 8) /* "its_native_only" CPU is affected by ITS, VMX…
557 #define X86_BUG_TSA X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transient Scheduler Attacks */
558 #define X86_BUG_VMSCAPE X86_BUG( 1*32+10) /* "vmscape" CPU is affected by VMSCAPE attacks from gu…