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/linux/include/math-emu/
H A Dop-4.h28 #define _FP_FRAC_DECL_4(X) _FP_W_TYPE X##_f[4] argument
31 D##_f[2] = S##_f[2], D##_f[3] = S##_f[3])
32 #define _FP_FRAC_SET_4(X,I) __FP_FRAC_SET_4(X, I) argument
33 #define _FP_FRAC_HIGH_4(X) (X##_f[3]) argument
34 #define _FP_FRAC_LOW_4(X) (X##_f[0]) argument
35 #define _FP_FRAC_WORD_4(X,w) (X##_f[w]) argument
37 #define _FP_FRAC_SLL_4(X,N) \ argument
44 for (_i = 3; _i >= _skip; --_i) \
45 X##_f[_i] = X##_f[_i-_skip]; \
48 for (_i = 3; _i > _skip; --_i) \
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_sf.h65 #define ROGUE_FW_SF_GID(x) (((u32)(x) >> 12) & 0xfU) argument
67 #define ROGUE_FW_SF_PARAMNUM(x) (((u32)(x) >> 16) & 0xfU) argument
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
82 "3D finished, HWRTData0State=%x, HWRTData1State=%x" },
83 { ROGUE_FW_LOG_CREATESFID(3, ROGUE_FW_GROUP_MAIN, 4),
84 "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d, prio: %d" },
86 "3D Transfer finished" },
87 { ROGUE_FW_LOG_CREATESFID(5, ROGUE_FW_GROUP_MAIN, 3),
88 "Kick Compute: FWCtx 0x%08.8x @ %d, prio: %d" },
92 … "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x. First kick:%d, Last kick:%d, CSW resume:%d, prio:%d" },
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot_rew.h13 #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16)) argument
15 #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16) argument
17 #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12)) argument
19 #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) argument
20 #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0)) argument
25 #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7)) argument
27 #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7) argument
28 #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5)) argument
30 #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5) argument
32 #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2)) argument
[all …]
H A Docelot_qs.h20 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) argument
24 #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
25 #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
26 #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) argument
34 #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) argument
36 #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) argument
37 #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) argument
39 #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) argument
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) argument
45 #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
[all …]
/linux/arch/csky/include/asm/
H A Duaccess.h11 #define __put_user_asm_b(x, ptr, err) \ argument
16 " br 3f \n" \
17 "2: mov %0, %3 \n" \
18 " br 3f \n" \
23 "3: \n" \
24 : "=r"(err), "=r"(x), "=r"(ptr), "=r"(errcode) \
25 : "0"(err), "1"(x), "2"(ptr), "3"(-EFAULT) \
29 #define __put_user_asm_h(x, ptr, err) \ argument
34 " br 3f \n" \
35 "2: mov %0, %3 \n" \
[all …]
/linux/drivers/comedi/drivers/
H A Dni_tio_internal.h14 #define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x)) argument
16 #define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x)) argument
21 #define GI_CNT_DIR(x) (((x) & 0x3) << 5) argument
22 #define GI_CNT_DIR_MASK GI_CNT_DIR(3)
32 #define NITIO_HW_SAVE_REG(x) (NITIO_G0_HW_SAVE + (x)) argument
33 #define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x)) argument
34 #define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x)) argument
35 #define GI_GATING_MODE(x) (((x) & 0x3) << 0) argument
39 #define GI_FALLING_EDGE_GATING GI_GATING_MODE(3)
40 #define GI_GATING_MODE_MASK GI_GATING_MODE(3)
[all …]
H A Dni_stc.h44 #define NISTC_INTB_ACK_REG 3
57 #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3)
79 #define NISTC_AI_CMD2_STOP_PULSE BIT(3)
85 #define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) argument
96 #define NISTC_AO_CMD2_MUTE_B BIT(3)
116 #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3)
134 #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
140 #define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) argument
142 #define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) argument
152 #define NISTC_DIO_CTRL_DIR(x) ((x) & 0xff) argument
[all …]
H A Dz8536.h15 #define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */
25 #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */
26 #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */
28 #define Z8536_CFG_CTRL_LC(x) (((x) & 0x3) << 0) /* Link Control */ argument
32 #define Z8536_CFG_CTRL_LC_CLK Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */
33 #define Z8536_CFG_CTRL_LC_MASK Z8536_CFG_CTRL_LC(3)
41 /* Port A/B & Counter/Timer 1/2/3 Command and Status registers */
47 #define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x)) argument
48 #define Z8536_CMD(x) (((x) & 0x7) << 5) argument
52 #define Z8536_CMD_CLR_IUS Z8536_CMD(3) /* Clear IUS */
[all …]
H A Daddi_tcw.h19 #define ADDI_TCW_SYNC_TIMER_ENA BIT(3)
33 #define ADDI_TCW_CTRL_EXT_CLK(x) (((x) & 3) << 16) argument
34 #define ADDI_TCW_CTRL_EXT_CLK_MASK ADDI_TCW_CTRL_EXT_CLK(3)
35 #define ADDI_TCW_CTRL_MODE(x) (((x) & 7) << 13) argument
37 #define ADDI_TCW_CTRL_OUT(x) (((x) & 3) << 11) argument
38 #define ADDI_TCW_CTRL_OUT_MASK ADDI_TCW_CTRL_OUT(3)
41 #define ADDI_TCW_CTRL_EXT_GATE(x) (((x) & 3) << 7) argument
42 #define ADDI_TCW_CTRL_EXT_GATE_MASK ADDI_TCW_CTRL_EXT_GATE(3)
43 #define ADDI_TCW_CTRL_EXT_TRIG(x) (((x) & 3) << 5) argument
44 #define ADDI_TCW_CTRL_EXT_TRIG_MASK ADDI_TCW_CTRL_EXT_TRIG(3)
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv6xxd.h34 # define THERMAL_PROTECTION_DIS (1 << 3)
37 # define SW_GPIO_INDEX(x) ((x) << 6) argument
38 # define SW_GPIO_INDEX_MASK (3 << 6)
51 # define SU_MCLK_USE_BCLK (1 << 3)
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) argument
81 # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) argument
83 # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) argument
90 # define VID_CRT(x) ((x) << 0) argument
92 # define VID_CRTU(x) ((x) << 13) argument
94 # define SSTU(x) ((x) << 16) argument
[all …]
H A Drv770d.h47 # define UPLL_REF_DIV(x) ((x) << 16) argument
52 # define UPLL_SW_HILEN(x) ((x) << 0) argument
53 # define UPLL_SW_LOLEN(x) ((x) << 4) argument
54 # define UPLL_SW_HILEN2(x) ((x) << 8) argument
55 # define UPLL_SW_LOLEN2(x) ((x) << 12) argument
57 # define VCLK_SRC_SEL(x) ((x) << 20) argument
59 # define DCLK_SRC_SEL(x) ((x) << 25) argument
62 # define UPLL_FB_DIV(x) ((x) << 0) argument
74 #define HOST_SMC_MSG(x) ((x) << 0) argument
77 #define HOST_SMC_RESP(x) ((x) << 8) argument
[all …]
H A Dcikd.h42 # define SamuBootLevel(x) ((x) << 0) argument
45 # define AcpBootLevel(x) ((x) << 8) argument
48 # define VceBootLevel(x) ((x) << 16) argument
51 # define UvdBootLevel(x) ((x) << 24) argument
59 # define Dpm0PgNbPsLo(x) ((x) << 0) argument
62 # define Dpm0PgNbPsHi(x) ((x) << 8) argument
65 # define DpmXNbPsLo(x) ((x) << 16) argument
68 # define DpmXNbPsHi(x) ((x) << 24) argument
93 # define THERMAL_PROTECTION_TYPE (1 << 3)
94 # define SW_SMIO_INDEX(x) ((x) << 6) argument
[all …]
/linux/include/soc/mscc/
H A Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14)) argument
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14) argument
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3)) argument
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
32 #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1)) argument
34 #define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1) argument
40 #define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12)) argument
[all …]
H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) argument
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) argument
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) argument
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) argument
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) argument
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) argument
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) argument
105 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) argument
106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
114 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) argument
[all …]
H A Docelot_qsys.h18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) argument
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) argument
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) argument
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
41 #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) argument
43 #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) argument
44 #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) argument
[all …]
/linux/crypto/
H A Dsm4.c72 static inline u32 sm4_t_non_lin_sub(u32 x) in sm4_t_non_lin_sub() argument
76 out = (u32)sbox[x & 0xff]; in sm4_t_non_lin_sub()
77 out |= (u32)sbox[(x >> 8) & 0xff] << 8; in sm4_t_non_lin_sub()
78 out |= (u32)sbox[(x >> 16) & 0xff] << 16; in sm4_t_non_lin_sub()
79 out |= (u32)sbox[(x >> 24) & 0xff] << 24; in sm4_t_non_lin_sub()
84 static inline u32 sm4_key_lin_sub(u32 x) in sm4_key_lin_sub() argument
86 return x ^ rol32(x, 13) ^ rol32(x, 23); in sm4_key_lin_sub()
89 static inline u32 sm4_enc_lin_sub(u32 x) in sm4_enc_lin_sub() argument
91 return x ^ rol32(x, 2) ^ rol32(x, 10) ^ rol32(x, 18) ^ rol32(x, 24); in sm4_enc_lin_sub()
94 static inline u32 sm4_key_sub(u32 x) in sm4_key_sub() argument
[all …]
/linux/sound/pci/ice1712/
H A Dhoontech.h30 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3)) argument
31 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2)) argument
32 #define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1)) argument
33 #define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1)) argument
34 #define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2)) argument
35 #define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1)) argument
36 #define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1)) argument
37 #define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2)) argument
38 #define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1)) argument
39 #define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1)) argument
[all …]
/linux/sound/soc/codecs/
H A Dcs42l51.h26 #define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b))
32 #define CS42L51_POWER_CTL1_PDN_PGAA (1<<3)
39 #define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) argument
40 #define CS42L51_QSM_MODE 3
45 #define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3)
53 #define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) argument
69 #define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) argument
78 #define CS42L51_ADC_CTL_SOFTB (1<<3)
84 #define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) argument
85 #define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) argument
[all …]
/linux/arch/sh/include/asm/
H A Duaccess_32.h16 #define __get_user_size(x,ptr,size,retval) \ argument
21 __get_user_asm(x, ptr, retval, "b"); \
24 __get_user_asm(x, ptr, retval, "w"); \
27 __get_user_asm(x, ptr, retval, "l"); \
30 __get_user_u64(x, ptr, retval); \
39 #define __get_user_asm(x, addr, err, insn) \ argument
46 "3:\n\t" \
50 " mov %3, %0\n\t" \
55 ".long 1b, 3b\n\t" \
57 :"=&r" (err), "=&r" (x) \
[all …]
/linux/Documentation/input/devices/
H A Dsentelic.rst20 3. Set sample rate to 80;
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
33 Bit6 => X overflow
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
59 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
61 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|r|l|u|d|
65 Bit6 => X overflow
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-fimc.h28 /* Y 3rd frame start address for output DMA */
36 /* Cb 3rd frame start address for output DMA */
44 /* Cr 3rd frame start address for output DMA */
321 #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) argument
322 #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) argument
324 #define EXYNOS_CIWDOFST_WINHOROFST(x) ((x) << 16) argument
325 #define EXYNOS_CIWDOFST_WINVEROFST(x) ((x) << 0) argument
327 #define EXYNOS_CIWDOFST2_WINHOROFST2(x) ((x) << 16) argument
328 #define EXYNOS_CIWDOFST2_WINVEROFST2(x) ((x) << 0) argument
330 #define EXYNOS_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16) argument
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h70 #define PIPEID(x) ((x) << 0) argument
71 #define MEID(x) ((x) << 2) argument
72 #define VMID(x) ((x) << 4) argument
73 #define QUEUEID(x) ((x) << 8) argument
90 #define PACKET_TYPE3 3
92 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
111 /* Packet 3 types */
114 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
115 #define CE_PARTITION_BASE 3
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1xxx_psc.h42 #define PSC_SEL_CLK_MASK (3 << 4)
50 #define PSC_SEL_PS_I2SMODE 3
56 #define PSC_CTRL_ENABLE 3
71 #define PSC_AC97CFG_RT_MASK (3 << 30)
75 #define PSC_AC97CFG_RT_FIFO8 (3 << 30)
77 #define PSC_AC97CFG_TT_MASK (3 << 28)
81 #define PSC_AC97CFG_TT_FIFO8 (3 << 28)
92 /* Enable slots 3-12. */
93 #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) argument
94 #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) argument
[all …]
/linux/lib/crypto/
H A Dchacha-block-generic.c18 u32 *x = state->x; in chacha_permute() local
25 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
26 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
27 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
28 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
30 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
31 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
32 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
33 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
35 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_genbus.h40 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
43 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
44 #define K_IO_WIDTH_SEL_4 3
45 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) argument
46 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) argument
50 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
54 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
62 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) argument
63 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) argument
71 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) argument
[all …]

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