1*081068fdSNicolas Frattaroli /* SPDX-License-Identifier: GPL-2.0-only */ 2*081068fdSNicolas Frattaroli /* 3*081068fdSNicolas Frattaroli * ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver 4*081068fdSNicolas Frattaroli * 5*081068fdSNicolas Frattaroli * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 6*081068fdSNicolas Frattaroli * Author: Sugar Zhang <sugar.zhang@rock-chips.com> 7*081068fdSNicolas Frattaroli * 8*081068fdSNicolas Frattaroli */ 9*081068fdSNicolas Frattaroli 10*081068fdSNicolas Frattaroli #ifndef _ROCKCHIP_I2S_TDM_H 11*081068fdSNicolas Frattaroli #define _ROCKCHIP_I2S_TDM_H 12*081068fdSNicolas Frattaroli 13*081068fdSNicolas Frattaroli /* 14*081068fdSNicolas Frattaroli * TXCR 15*081068fdSNicolas Frattaroli * transmit operation control register 16*081068fdSNicolas Frattaroli */ 17*081068fdSNicolas Frattaroli #define I2S_TXCR_PATH_SHIFT(x) (23 + (x) * 2) 18*081068fdSNicolas Frattaroli #define I2S_TXCR_PATH_MASK(x) (0x3 << I2S_TXCR_PATH_SHIFT(x)) 19*081068fdSNicolas Frattaroli #define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x)) 20*081068fdSNicolas Frattaroli #define I2S_TXCR_RCNT_SHIFT 17 21*081068fdSNicolas Frattaroli #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 22*081068fdSNicolas Frattaroli #define I2S_TXCR_CSR_SHIFT 15 23*081068fdSNicolas Frattaroli #define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT) 24*081068fdSNicolas Frattaroli #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 25*081068fdSNicolas Frattaroli #define I2S_TXCR_HWT BIT(14) 26*081068fdSNicolas Frattaroli #define I2S_TXCR_SJM_SHIFT 12 27*081068fdSNicolas Frattaroli #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 28*081068fdSNicolas Frattaroli #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 29*081068fdSNicolas Frattaroli #define I2S_TXCR_FBM_SHIFT 11 30*081068fdSNicolas Frattaroli #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 31*081068fdSNicolas Frattaroli #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 32*081068fdSNicolas Frattaroli #define I2S_TXCR_IBM_SHIFT 9 33*081068fdSNicolas Frattaroli #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 34*081068fdSNicolas Frattaroli #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 35*081068fdSNicolas Frattaroli #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 36*081068fdSNicolas Frattaroli #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 37*081068fdSNicolas Frattaroli #define I2S_TXCR_PBM_SHIFT 7 38*081068fdSNicolas Frattaroli #define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT) 39*081068fdSNicolas Frattaroli #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 40*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_SHIFT 5 41*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 42*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 43*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_TDM_PCM (2 << I2S_TXCR_TFS_SHIFT) 44*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_TDM_I2S (3 << I2S_TXCR_TFS_SHIFT) 45*081068fdSNicolas Frattaroli #define I2S_TXCR_TFS_MASK (3 << I2S_TXCR_TFS_SHIFT) 46*081068fdSNicolas Frattaroli #define I2S_TXCR_VDW_SHIFT 0 47*081068fdSNicolas Frattaroli #define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT) 48*081068fdSNicolas Frattaroli #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 49*081068fdSNicolas Frattaroli 50*081068fdSNicolas Frattaroli /* 51*081068fdSNicolas Frattaroli * RXCR 52*081068fdSNicolas Frattaroli * receive operation control register 53*081068fdSNicolas Frattaroli */ 54*081068fdSNicolas Frattaroli #define I2S_RXCR_PATH_SHIFT(x) (17 + (x) * 2) 55*081068fdSNicolas Frattaroli #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x)) 56*081068fdSNicolas Frattaroli #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x)) 57*081068fdSNicolas Frattaroli #define I2S_RXCR_CSR_SHIFT 15 58*081068fdSNicolas Frattaroli #define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT) 59*081068fdSNicolas Frattaroli #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 60*081068fdSNicolas Frattaroli #define I2S_RXCR_HWT BIT(14) 61*081068fdSNicolas Frattaroli #define I2S_RXCR_SJM_SHIFT 12 62*081068fdSNicolas Frattaroli #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 63*081068fdSNicolas Frattaroli #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 64*081068fdSNicolas Frattaroli #define I2S_RXCR_FBM_SHIFT 11 65*081068fdSNicolas Frattaroli #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 66*081068fdSNicolas Frattaroli #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 67*081068fdSNicolas Frattaroli #define I2S_RXCR_IBM_SHIFT 9 68*081068fdSNicolas Frattaroli #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 69*081068fdSNicolas Frattaroli #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 70*081068fdSNicolas Frattaroli #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 71*081068fdSNicolas Frattaroli #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 72*081068fdSNicolas Frattaroli #define I2S_RXCR_PBM_SHIFT 7 73*081068fdSNicolas Frattaroli #define I2S_RXCR_PBM_MODE(x) ((x) << I2S_RXCR_PBM_SHIFT) 74*081068fdSNicolas Frattaroli #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 75*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_SHIFT 5 76*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 77*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 78*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_TDM_PCM (2 << I2S_RXCR_TFS_SHIFT) 79*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_TDM_I2S (3 << I2S_RXCR_TFS_SHIFT) 80*081068fdSNicolas Frattaroli #define I2S_RXCR_TFS_MASK (3 << I2S_RXCR_TFS_SHIFT) 81*081068fdSNicolas Frattaroli #define I2S_RXCR_VDW_SHIFT 0 82*081068fdSNicolas Frattaroli #define I2S_RXCR_VDW(x) (((x) - 1) << I2S_RXCR_VDW_SHIFT) 83*081068fdSNicolas Frattaroli #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 84*081068fdSNicolas Frattaroli 85*081068fdSNicolas Frattaroli /* 86*081068fdSNicolas Frattaroli * CKR 87*081068fdSNicolas Frattaroli * clock generation register 88*081068fdSNicolas Frattaroli */ 89*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM_SHIFT 28 90*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT) 91*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) 92*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT) 93*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT) 94*081068fdSNicolas Frattaroli #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) 95*081068fdSNicolas Frattaroli #define I2S_CKR_MSS_SHIFT 27 96*081068fdSNicolas Frattaroli #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 97*081068fdSNicolas Frattaroli #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 98*081068fdSNicolas Frattaroli #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 99*081068fdSNicolas Frattaroli #define I2S_CKR_CKP_SHIFT 26 100*081068fdSNicolas Frattaroli #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT) 101*081068fdSNicolas Frattaroli #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT) 102*081068fdSNicolas Frattaroli #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) 103*081068fdSNicolas Frattaroli #define I2S_CKR_RLP_SHIFT 25 104*081068fdSNicolas Frattaroli #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 105*081068fdSNicolas Frattaroli #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT) 106*081068fdSNicolas Frattaroli #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT) 107*081068fdSNicolas Frattaroli #define I2S_CKR_TLP_SHIFT 24 108*081068fdSNicolas Frattaroli #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 109*081068fdSNicolas Frattaroli #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT) 110*081068fdSNicolas Frattaroli #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT) 111*081068fdSNicolas Frattaroli #define I2S_CKR_MDIV_SHIFT 16 112*081068fdSNicolas Frattaroli #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) 113*081068fdSNicolas Frattaroli #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 114*081068fdSNicolas Frattaroli #define I2S_CKR_RSD_SHIFT 8 115*081068fdSNicolas Frattaroli #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) 116*081068fdSNicolas Frattaroli #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 117*081068fdSNicolas Frattaroli #define I2S_CKR_TSD_SHIFT 0 118*081068fdSNicolas Frattaroli #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) 119*081068fdSNicolas Frattaroli #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 120*081068fdSNicolas Frattaroli 121*081068fdSNicolas Frattaroli /* 122*081068fdSNicolas Frattaroli * FIFOLR 123*081068fdSNicolas Frattaroli * FIFO level register 124*081068fdSNicolas Frattaroli */ 125*081068fdSNicolas Frattaroli #define I2S_FIFOLR_RFL_SHIFT 24 126*081068fdSNicolas Frattaroli #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) 127*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL3_SHIFT 18 128*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) 129*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL2_SHIFT 12 130*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) 131*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL1_SHIFT 6 132*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) 133*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL0_SHIFT 0 134*081068fdSNicolas Frattaroli #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) 135*081068fdSNicolas Frattaroli 136*081068fdSNicolas Frattaroli /* 137*081068fdSNicolas Frattaroli * DMACR 138*081068fdSNicolas Frattaroli * DMA control register 139*081068fdSNicolas Frattaroli */ 140*081068fdSNicolas Frattaroli #define I2S_DMACR_RDE_SHIFT 24 141*081068fdSNicolas Frattaroli #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 142*081068fdSNicolas Frattaroli #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 143*081068fdSNicolas Frattaroli #define I2S_DMACR_RDL_SHIFT 16 144*081068fdSNicolas Frattaroli #define I2S_DMACR_RDL(x) (((x) - 1) << I2S_DMACR_RDL_SHIFT) 145*081068fdSNicolas Frattaroli #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 146*081068fdSNicolas Frattaroli #define I2S_DMACR_TDE_SHIFT 8 147*081068fdSNicolas Frattaroli #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 148*081068fdSNicolas Frattaroli #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 149*081068fdSNicolas Frattaroli #define I2S_DMACR_TDL_SHIFT 0 150*081068fdSNicolas Frattaroli #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 151*081068fdSNicolas Frattaroli #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 152*081068fdSNicolas Frattaroli 153*081068fdSNicolas Frattaroli /* 154*081068fdSNicolas Frattaroli * INTCR 155*081068fdSNicolas Frattaroli * interrupt control register 156*081068fdSNicolas Frattaroli */ 157*081068fdSNicolas Frattaroli #define I2S_INTCR_RFT_SHIFT 20 158*081068fdSNicolas Frattaroli #define I2S_INTCR_RFT(x) (((x) - 1) << I2S_INTCR_RFT_SHIFT) 159*081068fdSNicolas Frattaroli #define I2S_INTCR_RXOIC BIT(18) 160*081068fdSNicolas Frattaroli #define I2S_INTCR_RXOIE_SHIFT 17 161*081068fdSNicolas Frattaroli #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) 162*081068fdSNicolas Frattaroli #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) 163*081068fdSNicolas Frattaroli #define I2S_INTCR_RXFIE_SHIFT 16 164*081068fdSNicolas Frattaroli #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) 165*081068fdSNicolas Frattaroli #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) 166*081068fdSNicolas Frattaroli #define I2S_INTCR_TFT_SHIFT 4 167*081068fdSNicolas Frattaroli #define I2S_INTCR_TFT(x) (((x) - 1) << I2S_INTCR_TFT_SHIFT) 168*081068fdSNicolas Frattaroli #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) 169*081068fdSNicolas Frattaroli #define I2S_INTCR_TXUIC BIT(2) 170*081068fdSNicolas Frattaroli #define I2S_INTCR_TXUIE_SHIFT 1 171*081068fdSNicolas Frattaroli #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) 172*081068fdSNicolas Frattaroli #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) 173*081068fdSNicolas Frattaroli 174*081068fdSNicolas Frattaroli /* 175*081068fdSNicolas Frattaroli * INTSR 176*081068fdSNicolas Frattaroli * interrupt status register 177*081068fdSNicolas Frattaroli */ 178*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEIE_SHIFT 0 179*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) 180*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) 181*081068fdSNicolas Frattaroli #define I2S_INTSR_RXOI_SHIFT 17 182*081068fdSNicolas Frattaroli #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) 183*081068fdSNicolas Frattaroli #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) 184*081068fdSNicolas Frattaroli #define I2S_INTSR_RXFI_SHIFT 16 185*081068fdSNicolas Frattaroli #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) 186*081068fdSNicolas Frattaroli #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) 187*081068fdSNicolas Frattaroli #define I2S_INTSR_TXUI_SHIFT 1 188*081068fdSNicolas Frattaroli #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) 189*081068fdSNicolas Frattaroli #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) 190*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEI_SHIFT 0 191*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) 192*081068fdSNicolas Frattaroli #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) 193*081068fdSNicolas Frattaroli 194*081068fdSNicolas Frattaroli /* 195*081068fdSNicolas Frattaroli * XFER 196*081068fdSNicolas Frattaroli * Transfer start register 197*081068fdSNicolas Frattaroli */ 198*081068fdSNicolas Frattaroli #define I2S_XFER_RXS_SHIFT 1 199*081068fdSNicolas Frattaroli #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 200*081068fdSNicolas Frattaroli #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 201*081068fdSNicolas Frattaroli #define I2S_XFER_TXS_SHIFT 0 202*081068fdSNicolas Frattaroli #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 203*081068fdSNicolas Frattaroli #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 204*081068fdSNicolas Frattaroli 205*081068fdSNicolas Frattaroli /* 206*081068fdSNicolas Frattaroli * CLR 207*081068fdSNicolas Frattaroli * clear SCLK domain logic register 208*081068fdSNicolas Frattaroli */ 209*081068fdSNicolas Frattaroli #define I2S_CLR_RXC BIT(1) 210*081068fdSNicolas Frattaroli #define I2S_CLR_TXC BIT(0) 211*081068fdSNicolas Frattaroli 212*081068fdSNicolas Frattaroli /* 213*081068fdSNicolas Frattaroli * TXDR 214*081068fdSNicolas Frattaroli * Transimt FIFO data register, write only. 215*081068fdSNicolas Frattaroli */ 216*081068fdSNicolas Frattaroli #define I2S_TXDR_MASK (0xff) 217*081068fdSNicolas Frattaroli 218*081068fdSNicolas Frattaroli /* 219*081068fdSNicolas Frattaroli * RXDR 220*081068fdSNicolas Frattaroli * Receive FIFO data register, write only. 221*081068fdSNicolas Frattaroli */ 222*081068fdSNicolas Frattaroli #define I2S_RXDR_MASK (0xff) 223*081068fdSNicolas Frattaroli 224*081068fdSNicolas Frattaroli /* 225*081068fdSNicolas Frattaroli * TDM_CTRL 226*081068fdSNicolas Frattaroli * TDM ctrl register 227*081068fdSNicolas Frattaroli */ 228*081068fdSNicolas Frattaroli #define TDM_FSYNC_WIDTH_SEL1_MSK GENMASK(20, 18) 229*081068fdSNicolas Frattaroli #define TDM_FSYNC_WIDTH_SEL1(x) (((x) - 1) << 18) 230*081068fdSNicolas Frattaroli #define TDM_FSYNC_WIDTH_SEL0_MSK BIT(17) 231*081068fdSNicolas Frattaroli #define TDM_FSYNC_WIDTH_HALF_FRAME 0 232*081068fdSNicolas Frattaroli #define TDM_FSYNC_WIDTH_ONE_FRAME BIT(17) 233*081068fdSNicolas Frattaroli #define TDM_SHIFT_CTRL_MSK GENMASK(16, 14) 234*081068fdSNicolas Frattaroli #define TDM_SHIFT_CTRL(x) ((x) << 14) 235*081068fdSNicolas Frattaroli #define TDM_SLOT_BIT_WIDTH_MSK GENMASK(13, 9) 236*081068fdSNicolas Frattaroli #define TDM_SLOT_BIT_WIDTH(x) (((x) - 1) << 9) 237*081068fdSNicolas Frattaroli #define TDM_FRAME_WIDTH_MSK GENMASK(8, 0) 238*081068fdSNicolas Frattaroli #define TDM_FRAME_WIDTH(x) (((x) - 1) << 0) 239*081068fdSNicolas Frattaroli 240*081068fdSNicolas Frattaroli /* 241*081068fdSNicolas Frattaroli * CLKDIV 242*081068fdSNicolas Frattaroli * Mclk div register 243*081068fdSNicolas Frattaroli */ 244*081068fdSNicolas Frattaroli #define I2S_CLKDIV_TXM_SHIFT 0 245*081068fdSNicolas Frattaroli #define I2S_CLKDIV_TXM(x) (((x) - 1) << I2S_CLKDIV_TXM_SHIFT) 246*081068fdSNicolas Frattaroli #define I2S_CLKDIV_TXM_MASK (0xff << I2S_CLKDIV_TXM_SHIFT) 247*081068fdSNicolas Frattaroli #define I2S_CLKDIV_RXM_SHIFT 8 248*081068fdSNicolas Frattaroli #define I2S_CLKDIV_RXM(x) (((x) - 1) << I2S_CLKDIV_RXM_SHIFT) 249*081068fdSNicolas Frattaroli #define I2S_CLKDIV_RXM_MASK (0xff << I2S_CLKDIV_RXM_SHIFT) 250*081068fdSNicolas Frattaroli 251*081068fdSNicolas Frattaroli /* Clock divider id */ 252*081068fdSNicolas Frattaroli enum { 253*081068fdSNicolas Frattaroli ROCKCHIP_DIV_MCLK = 0, 254*081068fdSNicolas Frattaroli ROCKCHIP_DIV_BCLK, 255*081068fdSNicolas Frattaroli }; 256*081068fdSNicolas Frattaroli 257*081068fdSNicolas Frattaroli /* channel select */ 258*081068fdSNicolas Frattaroli #define I2S_CSR_SHIFT 15 259*081068fdSNicolas Frattaroli #define I2S_CHN_2 (0 << I2S_CSR_SHIFT) 260*081068fdSNicolas Frattaroli #define I2S_CHN_4 (1 << I2S_CSR_SHIFT) 261*081068fdSNicolas Frattaroli #define I2S_CHN_6 (2 << I2S_CSR_SHIFT) 262*081068fdSNicolas Frattaroli #define I2S_CHN_8 (3 << I2S_CSR_SHIFT) 263*081068fdSNicolas Frattaroli 264*081068fdSNicolas Frattaroli /* io direction cfg register */ 265*081068fdSNicolas Frattaroli #define I2S_IO_DIRECTION_MASK (7) 266*081068fdSNicolas Frattaroli #define I2S_IO_8CH_OUT_2CH_IN (7) 267*081068fdSNicolas Frattaroli #define I2S_IO_6CH_OUT_4CH_IN (3) 268*081068fdSNicolas Frattaroli #define I2S_IO_4CH_OUT_6CH_IN (1) 269*081068fdSNicolas Frattaroli #define I2S_IO_2CH_OUT_8CH_IN (0) 270*081068fdSNicolas Frattaroli 271*081068fdSNicolas Frattaroli /* I2S REGS */ 272*081068fdSNicolas Frattaroli #define I2S_TXCR (0x0000) 273*081068fdSNicolas Frattaroli #define I2S_RXCR (0x0004) 274*081068fdSNicolas Frattaroli #define I2S_CKR (0x0008) 275*081068fdSNicolas Frattaroli #define I2S_TXFIFOLR (0x000c) 276*081068fdSNicolas Frattaroli #define I2S_DMACR (0x0010) 277*081068fdSNicolas Frattaroli #define I2S_INTCR (0x0014) 278*081068fdSNicolas Frattaroli #define I2S_INTSR (0x0018) 279*081068fdSNicolas Frattaroli #define I2S_XFER (0x001c) 280*081068fdSNicolas Frattaroli #define I2S_CLR (0x0020) 281*081068fdSNicolas Frattaroli #define I2S_TXDR (0x0024) 282*081068fdSNicolas Frattaroli #define I2S_RXDR (0x0028) 283*081068fdSNicolas Frattaroli #define I2S_RXFIFOLR (0x002c) 284*081068fdSNicolas Frattaroli #define I2S_TDM_TXCR (0x0030) 285*081068fdSNicolas Frattaroli #define I2S_TDM_RXCR (0x0034) 286*081068fdSNicolas Frattaroli #define I2S_CLKDIV (0x0038) 287*081068fdSNicolas Frattaroli 288*081068fdSNicolas Frattaroli #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 289*081068fdSNicolas Frattaroli 290*081068fdSNicolas Frattaroli /* PX30 GRF CONFIGS */ 291*081068fdSNicolas Frattaroli #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12) 292*081068fdSNicolas Frattaroli #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12) 293*081068fdSNicolas Frattaroli #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5) 294*081068fdSNicolas Frattaroli #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5) 295*081068fdSNicolas Frattaroli 296*081068fdSNicolas Frattaroli #define PX30_I2S0_CLK_TXONLY \ 297*081068fdSNicolas Frattaroli (PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX) 298*081068fdSNicolas Frattaroli 299*081068fdSNicolas Frattaroli #define PX30_I2S0_CLK_RXONLY \ 300*081068fdSNicolas Frattaroli (PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX) 301*081068fdSNicolas Frattaroli 302*081068fdSNicolas Frattaroli /* RK1808 GRF CONFIGS */ 303*081068fdSNicolas Frattaroli #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2) 304*081068fdSNicolas Frattaroli #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2) 305*081068fdSNicolas Frattaroli #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0) 306*081068fdSNicolas Frattaroli #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0) 307*081068fdSNicolas Frattaroli 308*081068fdSNicolas Frattaroli #define RK1808_I2S0_CLK_TXONLY \ 309*081068fdSNicolas Frattaroli (RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX) 310*081068fdSNicolas Frattaroli 311*081068fdSNicolas Frattaroli #define RK1808_I2S0_CLK_RXONLY \ 312*081068fdSNicolas Frattaroli (RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX) 313*081068fdSNicolas Frattaroli 314*081068fdSNicolas Frattaroli /* RK3308 GRF CONFIGS */ 315*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10) 316*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10) 317*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9) 318*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9) 319*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8) 320*081068fdSNicolas Frattaroli #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8) 321*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2) 322*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2) 323*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1) 324*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1) 325*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0) 326*081068fdSNicolas Frattaroli #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0) 327*081068fdSNicolas Frattaroli 328*081068fdSNicolas Frattaroli #define RK3308_I2S0_CLK_TXONLY \ 329*081068fdSNicolas Frattaroli (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \ 330*081068fdSNicolas Frattaroli RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \ 331*081068fdSNicolas Frattaroli RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX) 332*081068fdSNicolas Frattaroli 333*081068fdSNicolas Frattaroli #define RK3308_I2S0_CLK_RXONLY \ 334*081068fdSNicolas Frattaroli (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \ 335*081068fdSNicolas Frattaroli RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \ 336*081068fdSNicolas Frattaroli RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX) 337*081068fdSNicolas Frattaroli 338*081068fdSNicolas Frattaroli #define RK3308_I2S1_CLK_TXONLY \ 339*081068fdSNicolas Frattaroli (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \ 340*081068fdSNicolas Frattaroli RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \ 341*081068fdSNicolas Frattaroli RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX) 342*081068fdSNicolas Frattaroli 343*081068fdSNicolas Frattaroli #define RK3308_I2S1_CLK_RXONLY \ 344*081068fdSNicolas Frattaroli (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \ 345*081068fdSNicolas Frattaroli RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \ 346*081068fdSNicolas Frattaroli RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX) 347*081068fdSNicolas Frattaroli 348*081068fdSNicolas Frattaroli /* RK3568 GRF CONFIGS */ 349*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5) 350*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5) 351*081068fdSNicolas Frattaroli 352*081068fdSNicolas Frattaroli #define RK3568_I2S1_CLK_TXONLY \ 353*081068fdSNicolas Frattaroli RK3568_I2S1_MCLK_OUT_SRC_FROM_TX 354*081068fdSNicolas Frattaroli 355*081068fdSNicolas Frattaroli #define RK3568_I2S1_CLK_RXONLY \ 356*081068fdSNicolas Frattaroli RK3568_I2S1_MCLK_OUT_SRC_FROM_RX 357*081068fdSNicolas Frattaroli 358*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 15, 15) 359*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 15, 15) 360*081068fdSNicolas Frattaroli #define RK3568_I2S3_SCLK_SRC_FROM_TX HIWORD_UPDATE(1, 7, 7) 361*081068fdSNicolas Frattaroli #define RK3568_I2S3_SCLK_SRC_FROM_RX HIWORD_UPDATE(0, 7, 7) 362*081068fdSNicolas Frattaroli #define RK3568_I2S3_LRCK_SRC_FROM_TX HIWORD_UPDATE(1, 6, 6) 363*081068fdSNicolas Frattaroli #define RK3568_I2S3_LRCK_SRC_FROM_RX HIWORD_UPDATE(0, 6, 6) 364*081068fdSNicolas Frattaroli 365*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_TXONLY \ 366*081068fdSNicolas Frattaroli RK3568_I2S3_MCLK_OUT_SRC_FROM_TX 367*081068fdSNicolas Frattaroli 368*081068fdSNicolas Frattaroli #define RK3568_I2S3_CLK_TXONLY \ 369*081068fdSNicolas Frattaroli (RK3568_I2S3_SCLK_SRC_FROM_TX | \ 370*081068fdSNicolas Frattaroli RK3568_I2S3_LRCK_SRC_FROM_TX) 371*081068fdSNicolas Frattaroli 372*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_RXONLY \ 373*081068fdSNicolas Frattaroli RK3568_I2S3_MCLK_OUT_SRC_FROM_RX 374*081068fdSNicolas Frattaroli 375*081068fdSNicolas Frattaroli #define RK3568_I2S3_CLK_RXONLY \ 376*081068fdSNicolas Frattaroli (RK3568_I2S3_SCLK_SRC_FROM_RX | \ 377*081068fdSNicolas Frattaroli RK3568_I2S3_LRCK_SRC_FROM_RX) 378*081068fdSNicolas Frattaroli 379*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_IE HIWORD_UPDATE(0, 3, 3) 380*081068fdSNicolas Frattaroli #define RK3568_I2S3_MCLK_OE HIWORD_UPDATE(1, 3, 3) 381*081068fdSNicolas Frattaroli #define RK3568_I2S2_MCLK_IE HIWORD_UPDATE(0, 2, 2) 382*081068fdSNicolas Frattaroli #define RK3568_I2S2_MCLK_OE HIWORD_UPDATE(1, 2, 2) 383*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_TX_IE HIWORD_UPDATE(0, 1, 1) 384*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_TX_OE HIWORD_UPDATE(1, 1, 1) 385*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_RX_IE HIWORD_UPDATE(0, 0, 0) 386*081068fdSNicolas Frattaroli #define RK3568_I2S1_MCLK_RX_OE HIWORD_UPDATE(1, 0, 0) 387*081068fdSNicolas Frattaroli 388*081068fdSNicolas Frattaroli /* RV1126 GRF CONFIGS */ 389*081068fdSNicolas Frattaroli #define RV1126_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 9, 9) 390*081068fdSNicolas Frattaroli #define RV1126_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 9, 9) 391*081068fdSNicolas Frattaroli 392*081068fdSNicolas Frattaroli #define RV1126_I2S0_CLK_TXONLY \ 393*081068fdSNicolas Frattaroli RV1126_I2S0_MCLK_OUT_SRC_FROM_TX 394*081068fdSNicolas Frattaroli 395*081068fdSNicolas Frattaroli #define RV1126_I2S0_CLK_RXONLY \ 396*081068fdSNicolas Frattaroli RV1126_I2S0_MCLK_OUT_SRC_FROM_RX 397*081068fdSNicolas Frattaroli 398*081068fdSNicolas Frattaroli #endif /* _ROCKCHIP_I2S_TDM_H */ 399