18cc1a532SAlex Deucher /* 28cc1a532SAlex Deucher * Copyright 2012 Advanced Micro Devices, Inc. 38cc1a532SAlex Deucher * 48cc1a532SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 58cc1a532SAlex Deucher * copy of this software and associated documentation files (the "Software"), 68cc1a532SAlex Deucher * to deal in the Software without restriction, including without limitation 78cc1a532SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88cc1a532SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 98cc1a532SAlex Deucher * Software is furnished to do so, subject to the following conditions: 108cc1a532SAlex Deucher * 118cc1a532SAlex Deucher * The above copyright notice and this permission notice shall be included in 128cc1a532SAlex Deucher * all copies or substantial portions of the Software. 138cc1a532SAlex Deucher * 148cc1a532SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158cc1a532SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168cc1a532SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178cc1a532SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 188cc1a532SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 198cc1a532SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 208cc1a532SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 218cc1a532SAlex Deucher * 228cc1a532SAlex Deucher * Authors: Alex Deucher 238cc1a532SAlex Deucher */ 248cc1a532SAlex Deucher #ifndef CIK_H 258cc1a532SAlex Deucher #define CIK_H 268cc1a532SAlex Deucher 278cc1a532SAlex Deucher #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 28b496038bSAlex Deucher #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 298cc1a532SAlex Deucher 308cc1a532SAlex Deucher #define CIK_RB_BITMAP_WIDTH_PER_SH 2 31fc821b70SAlex Deucher #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 328cc1a532SAlex Deucher 3341a524abSAlex Deucher /* DIDT IND registers */ 3441a524abSAlex Deucher #define DIDT_SQ_CTRL0 0x0 3541a524abSAlex Deucher # define DIDT_CTRL_EN (1 << 0) 3641a524abSAlex Deucher #define DIDT_DB_CTRL0 0x20 3741a524abSAlex Deucher #define DIDT_TD_CTRL0 0x40 3841a524abSAlex Deucher #define DIDT_TCP_CTRL0 0x60 3941a524abSAlex Deucher 402c67912cSAlex Deucher /* SMC IND registers */ 41cc8dbbb4SAlex Deucher #define DPM_TABLE_475 0x3F768 42cc8dbbb4SAlex Deucher # define SamuBootLevel(x) ((x) << 0) 43cc8dbbb4SAlex Deucher # define SamuBootLevel_MASK 0x000000ff 44cc8dbbb4SAlex Deucher # define SamuBootLevel_SHIFT 0 45cc8dbbb4SAlex Deucher # define AcpBootLevel(x) ((x) << 8) 46cc8dbbb4SAlex Deucher # define AcpBootLevel_MASK 0x0000ff00 47cc8dbbb4SAlex Deucher # define AcpBootLevel_SHIFT 8 48cc8dbbb4SAlex Deucher # define VceBootLevel(x) ((x) << 16) 49cc8dbbb4SAlex Deucher # define VceBootLevel_MASK 0x00ff0000 50cc8dbbb4SAlex Deucher # define VceBootLevel_SHIFT 16 51cc8dbbb4SAlex Deucher # define UvdBootLevel(x) ((x) << 24) 52cc8dbbb4SAlex Deucher # define UvdBootLevel_MASK 0xff000000 53cc8dbbb4SAlex Deucher # define UvdBootLevel_SHIFT 24 54cc8dbbb4SAlex Deucher 55cc8dbbb4SAlex Deucher #define FIRMWARE_FLAGS 0x3F800 56cc8dbbb4SAlex Deucher # define INTERRUPTS_ENABLED (1 << 0) 57cc8dbbb4SAlex Deucher 5841a524abSAlex Deucher #define NB_DPM_CONFIG_1 0x3F9E8 5941a524abSAlex Deucher # define Dpm0PgNbPsLo(x) ((x) << 0) 6041a524abSAlex Deucher # define Dpm0PgNbPsLo_MASK 0x000000ff 6141a524abSAlex Deucher # define Dpm0PgNbPsLo_SHIFT 0 6241a524abSAlex Deucher # define Dpm0PgNbPsHi(x) ((x) << 8) 6341a524abSAlex Deucher # define Dpm0PgNbPsHi_MASK 0x0000ff00 6441a524abSAlex Deucher # define Dpm0PgNbPsHi_SHIFT 8 6541a524abSAlex Deucher # define DpmXNbPsLo(x) ((x) << 16) 6641a524abSAlex Deucher # define DpmXNbPsLo_MASK 0x00ff0000 6741a524abSAlex Deucher # define DpmXNbPsLo_SHIFT 16 6841a524abSAlex Deucher # define DpmXNbPsHi(x) ((x) << 24) 6941a524abSAlex Deucher # define DpmXNbPsHi_MASK 0xff000000 7041a524abSAlex Deucher # define DpmXNbPsHi_SHIFT 24 7141a524abSAlex Deucher 72cc8dbbb4SAlex Deucher #define SMC_SYSCON_RESET_CNTL 0x80000000 73cc8dbbb4SAlex Deucher # define RST_REG (1 << 0) 74cc8dbbb4SAlex Deucher #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 75cc8dbbb4SAlex Deucher # define CK_DISABLE (1 << 0) 76cc8dbbb4SAlex Deucher # define CKEN (1 << 24) 77cc8dbbb4SAlex Deucher 78cc8dbbb4SAlex Deucher #define SMC_SYSCON_MISC_CNTL 0x80000010 79cc8dbbb4SAlex Deucher 8041a524abSAlex Deucher #define SMC_SYSCON_MSG_ARG_0 0x80000068 8141a524abSAlex Deucher 82cc8dbbb4SAlex Deucher #define SMC_PC_C 0x80000370 83cc8dbbb4SAlex Deucher 84cc8dbbb4SAlex Deucher #define SMC_SCRATCH9 0x80000424 85cc8dbbb4SAlex Deucher 86cc8dbbb4SAlex Deucher #define RCU_UC_EVENTS 0xC0000004 87cc8dbbb4SAlex Deucher # define BOOT_SEQ_DONE (1 << 7) 88cc8dbbb4SAlex Deucher 892c67912cSAlex Deucher #define GENERAL_PWRMGT 0xC0200000 9041a524abSAlex Deucher # define GLOBAL_PWRMGT_EN (1 << 0) 91cc8dbbb4SAlex Deucher # define STATIC_PM_EN (1 << 1) 92cc8dbbb4SAlex Deucher # define THERMAL_PROTECTION_DIS (1 << 2) 93cc8dbbb4SAlex Deucher # define THERMAL_PROTECTION_TYPE (1 << 3) 94cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX(x) ((x) << 6) 95cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX_MASK (1 << 6) 96cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX_SHIFT 6 97cc8dbbb4SAlex Deucher # define VOLT_PWRMGT_EN (1 << 10) 982c67912cSAlex Deucher # define GPU_COUNTER_CLK (1 << 15) 99cc8dbbb4SAlex Deucher # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 100cc8dbbb4SAlex Deucher 101cc8dbbb4SAlex Deucher #define CNB_PWRMGT_CNTL 0xC0200004 102cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE(x) ((x) << 0) 103cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE_MASK (3 << 0) 104cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE_SHIFT 0 105cc8dbbb4SAlex Deucher # define GNB_SLOW (1 << 2) 106cc8dbbb4SAlex Deucher # define FORCE_NB_PS1 (1 << 3) 107cc8dbbb4SAlex Deucher # define DPM_ENABLED (1 << 4) 1082c67912cSAlex Deucher 10941a524abSAlex Deucher #define SCLK_PWRMGT_CNTL 0xC0200008 110cc8dbbb4SAlex Deucher # define SCLK_PWRMGT_OFF (1 << 0) 11141a524abSAlex Deucher # define RESET_BUSY_CNT (1 << 4) 11241a524abSAlex Deucher # define RESET_SCLK_CNT (1 << 5) 11341a524abSAlex Deucher # define DYNAMIC_PM_EN (1 << 21) 11441a524abSAlex Deucher 11594b4adc5SAlex Deucher #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 11694b4adc5SAlex Deucher # define CURRENT_STATE_MASK (0xf << 4) 11794b4adc5SAlex Deucher # define CURRENT_STATE_SHIFT 4 11894b4adc5SAlex Deucher # define CURR_MCLK_INDEX_MASK (0xf << 8) 11994b4adc5SAlex Deucher # define CURR_MCLK_INDEX_SHIFT 8 12094b4adc5SAlex Deucher # define CURR_SCLK_INDEX_MASK (0x1f << 16) 12194b4adc5SAlex Deucher # define CURR_SCLK_INDEX_SHIFT 16 12294b4adc5SAlex Deucher 123cc8dbbb4SAlex Deucher #define CG_SSP 0xC0200044 124cc8dbbb4SAlex Deucher # define SST(x) ((x) << 0) 125cc8dbbb4SAlex Deucher # define SST_MASK (0xffff << 0) 126cc8dbbb4SAlex Deucher # define SSTU(x) ((x) << 16) 127cc8dbbb4SAlex Deucher # define SSTU_MASK (0xf << 16) 128cc8dbbb4SAlex Deucher 129cc8dbbb4SAlex Deucher #define CG_DISPLAY_GAP_CNTL 0xC0200060 130cc8dbbb4SAlex Deucher # define DISP_GAP(x) ((x) << 0) 131cc8dbbb4SAlex Deucher # define DISP_GAP_MASK (3 << 0) 132cc8dbbb4SAlex Deucher # define VBI_TIMER_COUNT(x) ((x) << 4) 133cc8dbbb4SAlex Deucher # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 134cc8dbbb4SAlex Deucher # define VBI_TIMER_UNIT(x) ((x) << 20) 135cc8dbbb4SAlex Deucher # define VBI_TIMER_UNIT_MASK (7 << 20) 136cc8dbbb4SAlex Deucher # define DISP_GAP_MCHG(x) ((x) << 24) 137cc8dbbb4SAlex Deucher # define DISP_GAP_MCHG_MASK (3 << 24) 138cc8dbbb4SAlex Deucher 139ae3e40e8SAlex Deucher #define SMU_VOLTAGE_STATUS 0xC0200094 140ae3e40e8SAlex Deucher # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 141ae3e40e8SAlex Deucher # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 142ae3e40e8SAlex Deucher 14394b4adc5SAlex Deucher #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 14494b4adc5SAlex Deucher # define CURR_PCIE_INDEX_MASK (0xf << 24) 14594b4adc5SAlex Deucher # define CURR_PCIE_INDEX_SHIFT 24 14694b4adc5SAlex Deucher 147cc8dbbb4SAlex Deucher #define CG_ULV_PARAMETER 0xC0200158 148cc8dbbb4SAlex Deucher 14941a524abSAlex Deucher #define CG_FTV_0 0xC02001A8 150cc8dbbb4SAlex Deucher #define CG_FTV_1 0xC02001AC 151cc8dbbb4SAlex Deucher #define CG_FTV_2 0xC02001B0 152cc8dbbb4SAlex Deucher #define CG_FTV_3 0xC02001B4 153cc8dbbb4SAlex Deucher #define CG_FTV_4 0xC02001B8 154cc8dbbb4SAlex Deucher #define CG_FTV_5 0xC02001BC 155cc8dbbb4SAlex Deucher #define CG_FTV_6 0xC02001C0 156cc8dbbb4SAlex Deucher #define CG_FTV_7 0xC02001C4 157cc8dbbb4SAlex Deucher 158cc8dbbb4SAlex Deucher #define CG_DISPLAY_GAP_CNTL2 0xC0200230 15941a524abSAlex Deucher 16041a524abSAlex Deucher #define LCAC_SX0_OVR_SEL 0xC0400D04 16141a524abSAlex Deucher #define LCAC_SX0_OVR_VAL 0xC0400D08 16241a524abSAlex Deucher 163cc8dbbb4SAlex Deucher #define LCAC_MC0_CNTL 0xC0400D30 16441a524abSAlex Deucher #define LCAC_MC0_OVR_SEL 0xC0400D34 16541a524abSAlex Deucher #define LCAC_MC0_OVR_VAL 0xC0400D38 166cc8dbbb4SAlex Deucher #define LCAC_MC1_CNTL 0xC0400D3C 16741a524abSAlex Deucher #define LCAC_MC1_OVR_SEL 0xC0400D40 16841a524abSAlex Deucher #define LCAC_MC1_OVR_VAL 0xC0400D44 16941a524abSAlex Deucher 17041a524abSAlex Deucher #define LCAC_MC2_OVR_SEL 0xC0400D4C 17141a524abSAlex Deucher #define LCAC_MC2_OVR_VAL 0xC0400D50 17241a524abSAlex Deucher 17341a524abSAlex Deucher #define LCAC_MC3_OVR_SEL 0xC0400D58 17441a524abSAlex Deucher #define LCAC_MC3_OVR_VAL 0xC0400D5C 17541a524abSAlex Deucher 176cc8dbbb4SAlex Deucher #define LCAC_CPL_CNTL 0xC0400D80 17741a524abSAlex Deucher #define LCAC_CPL_OVR_SEL 0xC0400D84 17841a524abSAlex Deucher #define LCAC_CPL_OVR_VAL 0xC0400D88 17941a524abSAlex Deucher 180cc8dbbb4SAlex Deucher /* dGPU */ 181cc8dbbb4SAlex Deucher #define CG_THERMAL_CTRL 0xC0300004 182cc8dbbb4SAlex Deucher #define DPM_EVENT_SRC(x) ((x) << 0) 183cc8dbbb4SAlex Deucher #define DPM_EVENT_SRC_MASK (7 << 0) 184cc8dbbb4SAlex Deucher #define DIG_THERM_DPM(x) ((x) << 14) 185cc8dbbb4SAlex Deucher #define DIG_THERM_DPM_MASK 0x003FC000 186cc8dbbb4SAlex Deucher #define DIG_THERM_DPM_SHIFT 14 187e03cea36SAlex Deucher #define CG_THERMAL_STATUS 0xC0300008 188e03cea36SAlex Deucher #define FDO_PWM_DUTY(x) ((x) << 9) 189e03cea36SAlex Deucher #define FDO_PWM_DUTY_MASK (0xff << 9) 190e03cea36SAlex Deucher #define FDO_PWM_DUTY_SHIFT 9 191cc8dbbb4SAlex Deucher #define CG_THERMAL_INT 0xC030000C 192cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH(x) ((x) << 8) 193cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH_MASK 0x0000FF00 194cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH_SHIFT 8 195cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL(x) ((x) << 16) 196cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL_MASK 0x00FF0000 197cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL_SHIFT 16 198cc8dbbb4SAlex Deucher #define THERM_INT_MASK_HIGH (1 << 24) 199cc8dbbb4SAlex Deucher #define THERM_INT_MASK_LOW (1 << 25) 200e03cea36SAlex Deucher #define CG_MULT_THERMAL_CTRL 0xC0300010 201e03cea36SAlex Deucher #define TEMP_SEL(x) ((x) << 20) 202e03cea36SAlex Deucher #define TEMP_SEL_MASK (0xff << 20) 203e03cea36SAlex Deucher #define TEMP_SEL_SHIFT 20 204286d9cc6SAlex Deucher #define CG_MULT_THERMAL_STATUS 0xC0300014 205286d9cc6SAlex Deucher #define ASIC_MAX_TEMP(x) ((x) << 0) 206286d9cc6SAlex Deucher #define ASIC_MAX_TEMP_MASK 0x000001ff 207286d9cc6SAlex Deucher #define ASIC_MAX_TEMP_SHIFT 0 208286d9cc6SAlex Deucher #define CTF_TEMP(x) ((x) << 9) 209286d9cc6SAlex Deucher #define CTF_TEMP_MASK 0x0003fe00 210286d9cc6SAlex Deucher #define CTF_TEMP_SHIFT 9 211286d9cc6SAlex Deucher 212e03cea36SAlex Deucher #define CG_FDO_CTRL0 0xC0300064 213e03cea36SAlex Deucher #define FDO_STATIC_DUTY(x) ((x) << 0) 214ff4b4af1SAlex Deucher #define FDO_STATIC_DUTY_MASK 0x000000FF 215e03cea36SAlex Deucher #define FDO_STATIC_DUTY_SHIFT 0 216e03cea36SAlex Deucher #define CG_FDO_CTRL1 0xC0300068 217e03cea36SAlex Deucher #define FMAX_DUTY100(x) ((x) << 0) 218ff4b4af1SAlex Deucher #define FMAX_DUTY100_MASK 0x000000FF 219e03cea36SAlex Deucher #define FMAX_DUTY100_SHIFT 0 220e03cea36SAlex Deucher #define CG_FDO_CTRL2 0xC030006C 221e03cea36SAlex Deucher #define TMIN(x) ((x) << 0) 222ff4b4af1SAlex Deucher #define TMIN_MASK 0x000000FF 223e03cea36SAlex Deucher #define TMIN_SHIFT 0 224e03cea36SAlex Deucher #define FDO_PWM_MODE(x) ((x) << 11) 225ff4b4af1SAlex Deucher #define FDO_PWM_MODE_MASK (7 << 11) 226e03cea36SAlex Deucher #define FDO_PWM_MODE_SHIFT 11 227e03cea36SAlex Deucher #define TACH_PWM_RESP_RATE(x) ((x) << 25) 228e03cea36SAlex Deucher #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 229e03cea36SAlex Deucher #define TACH_PWM_RESP_RATE_SHIFT 25 230e03cea36SAlex Deucher #define CG_TACH_CTRL 0xC0300070 231e03cea36SAlex Deucher # define EDGE_PER_REV(x) ((x) << 0) 232e03cea36SAlex Deucher # define EDGE_PER_REV_MASK (0x7 << 0) 233e03cea36SAlex Deucher # define EDGE_PER_REV_SHIFT 0 234e03cea36SAlex Deucher # define TARGET_PERIOD(x) ((x) << 3) 235e03cea36SAlex Deucher # define TARGET_PERIOD_MASK 0xfffffff8 236e03cea36SAlex Deucher # define TARGET_PERIOD_SHIFT 3 237e03cea36SAlex Deucher #define CG_TACH_STATUS 0xC0300074 238e03cea36SAlex Deucher # define TACH_PERIOD(x) ((x) << 0) 239e03cea36SAlex Deucher # define TACH_PERIOD_MASK 0xffffffff 240e03cea36SAlex Deucher # define TACH_PERIOD_SHIFT 0 241e03cea36SAlex Deucher 2425ad6bf91SAlex Deucher #define CG_ECLK_CNTL 0xC05000AC 2435ad6bf91SAlex Deucher # define ECLK_DIVIDER_MASK 0x7f 2445ad6bf91SAlex Deucher # define ECLK_DIR_CNTL_EN (1 << 8) 2455ad6bf91SAlex Deucher #define CG_ECLK_STATUS 0xC05000B0 2465ad6bf91SAlex Deucher # define ECLK_STATUS (1 << 0) 2475ad6bf91SAlex Deucher 248cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL 0xC0500140 249cc8dbbb4SAlex Deucher #define SPLL_RESET (1 << 0) 250cc8dbbb4SAlex Deucher #define SPLL_PWRON (1 << 1) 251cc8dbbb4SAlex Deucher #define SPLL_BYPASS_EN (1 << 3) 252cc8dbbb4SAlex Deucher #define SPLL_REF_DIV(x) ((x) << 5) 253cc8dbbb4SAlex Deucher #define SPLL_REF_DIV_MASK (0x3f << 5) 254cc8dbbb4SAlex Deucher #define SPLL_PDIV_A(x) ((x) << 20) 255cc8dbbb4SAlex Deucher #define SPLL_PDIV_A_MASK (0x7f << 20) 256cc8dbbb4SAlex Deucher #define SPLL_PDIV_A_SHIFT 20 257cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_2 0xC0500144 258cc8dbbb4SAlex Deucher #define SCLK_MUX_SEL(x) ((x) << 0) 259cc8dbbb4SAlex Deucher #define SCLK_MUX_SEL_MASK (0x1ff << 0) 260cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_3 0xC0500148 261cc8dbbb4SAlex Deucher #define SPLL_FB_DIV(x) ((x) << 0) 262cc8dbbb4SAlex Deucher #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 263cc8dbbb4SAlex Deucher #define SPLL_FB_DIV_SHIFT 0 264cc8dbbb4SAlex Deucher #define SPLL_DITHEN (1 << 28) 265cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_4 0xC050014C 266cc8dbbb4SAlex Deucher 267cc8dbbb4SAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 268cc8dbbb4SAlex Deucher #define SSEN (1 << 0) 269cc8dbbb4SAlex Deucher #define CLK_S(x) ((x) << 4) 270cc8dbbb4SAlex Deucher #define CLK_S_MASK (0xfff << 4) 271cc8dbbb4SAlex Deucher #define CLK_S_SHIFT 4 272cc8dbbb4SAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 273cc8dbbb4SAlex Deucher #define CLK_V(x) ((x) << 0) 274cc8dbbb4SAlex Deucher #define CLK_V_MASK (0x3ffffff << 0) 275cc8dbbb4SAlex Deucher #define CLK_V_SHIFT 0 276cc8dbbb4SAlex Deucher 2777235711aSAlex Deucher #define MPLL_BYPASSCLK_SEL 0xC050019C 2787235711aSAlex Deucher # define MPLL_CLKOUT_SEL(x) ((x) << 8) 2797235711aSAlex Deucher # define MPLL_CLKOUT_SEL_MASK 0xFF00 2802c67912cSAlex Deucher #define CG_CLKPIN_CNTL 0xC05001A0 2812c67912cSAlex Deucher # define XTALIN_DIVIDE (1 << 1) 2827235711aSAlex Deucher # define BCLK_AS_XCLK (1 << 2) 2837235711aSAlex Deucher #define CG_CLKPIN_CNTL_2 0xC05001A4 2847235711aSAlex Deucher # define FORCE_BIF_REFCLK_EN (1 << 3) 2857235711aSAlex Deucher # define MUX_TCLK_TO_XCLK (1 << 8) 2867235711aSAlex Deucher #define THM_CLK_CNTL 0xC05001A8 2877235711aSAlex Deucher # define CMON_CLK_SEL(x) ((x) << 0) 2887235711aSAlex Deucher # define CMON_CLK_SEL_MASK 0xFF 2897235711aSAlex Deucher # define TMON_CLK_SEL(x) ((x) << 8) 2907235711aSAlex Deucher # define TMON_CLK_SEL_MASK 0xFF00 2917235711aSAlex Deucher #define MISC_CLK_CTRL 0xC05001AC 2927235711aSAlex Deucher # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 2937235711aSAlex Deucher # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 2947235711aSAlex Deucher # define ZCLK_SEL(x) ((x) << 8) 2957235711aSAlex Deucher # define ZCLK_SEL_MASK 0xFF00 2962c67912cSAlex Deucher 297cc8dbbb4SAlex Deucher /* KV/KB */ 29841a524abSAlex Deucher #define CG_THERMAL_INT_CTRL 0xC2100028 29941a524abSAlex Deucher #define DIG_THERM_INTH(x) ((x) << 0) 30041a524abSAlex Deucher #define DIG_THERM_INTH_MASK 0x000000FF 30141a524abSAlex Deucher #define DIG_THERM_INTH_SHIFT 0 30241a524abSAlex Deucher #define DIG_THERM_INTL(x) ((x) << 8) 30341a524abSAlex Deucher #define DIG_THERM_INTL_MASK 0x0000FF00 30441a524abSAlex Deucher #define DIG_THERM_INTL_SHIFT 8 30541a524abSAlex Deucher #define THERM_INTH_MASK (1 << 24) 30641a524abSAlex Deucher #define THERM_INTL_MASK (1 << 25) 30741a524abSAlex Deucher 3088a7cd276SAlex Deucher /* PCIE registers idx/data 0x38/0x3c */ 3097235711aSAlex Deucher #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 3107235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 3117235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 3127235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 3137235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 3147235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 3157235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 3167235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 3177235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 3187235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0_SHIFT 24 3197235711aSAlex Deucher #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 3207235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 3217235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 3227235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 3237235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 3247235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 3257235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 3267235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 3277235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 3287235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1_SHIFT 24 3297235711aSAlex Deucher 3307235711aSAlex Deucher #define PCIE_CNTL2 0x1001001c /* PCIE */ 3317235711aSAlex Deucher # define SLV_MEM_LS_EN (1 << 16) 332473359bcSAlex Deucher # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 3337235711aSAlex Deucher # define MST_MEM_LS_EN (1 << 18) 3347235711aSAlex Deucher # define REPLAY_MEM_LS_EN (1 << 19) 3357235711aSAlex Deucher 3368a7cd276SAlex Deucher #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 3378a7cd276SAlex Deucher # define LC_REVERSE_RCVR (1 << 0) 3388a7cd276SAlex Deucher # define LC_REVERSE_XMIT (1 << 1) 3398a7cd276SAlex Deucher # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 3408a7cd276SAlex Deucher # define LC_OPERATING_LINK_WIDTH_SHIFT 2 3418a7cd276SAlex Deucher # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 3428a7cd276SAlex Deucher # define LC_DETECTED_LINK_WIDTH_SHIFT 5 3438a7cd276SAlex Deucher 3447235711aSAlex Deucher #define PCIE_P_CNTL 0x1400040 /* PCIE */ 3457235711aSAlex Deucher # define P_IGNORE_EDB_ERR (1 << 6) 3467235711aSAlex Deucher 3477235711aSAlex Deucher #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 3487235711aSAlex Deucher #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 3497235711aSAlex Deucher 3507235711aSAlex Deucher #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 3517235711aSAlex Deucher # define LC_L0S_INACTIVITY(x) ((x) << 8) 3527235711aSAlex Deucher # define LC_L0S_INACTIVITY_MASK (0xf << 8) 3537235711aSAlex Deucher # define LC_L0S_INACTIVITY_SHIFT 8 3547235711aSAlex Deucher # define LC_L1_INACTIVITY(x) ((x) << 12) 3557235711aSAlex Deucher # define LC_L1_INACTIVITY_MASK (0xf << 12) 3567235711aSAlex Deucher # define LC_L1_INACTIVITY_SHIFT 12 3577235711aSAlex Deucher # define LC_PMI_TO_L1_DIS (1 << 16) 3587235711aSAlex Deucher # define LC_ASPM_TO_L1_DIS (1 << 24) 3597235711aSAlex Deucher 3608a7cd276SAlex Deucher #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 3618a7cd276SAlex Deucher # define LC_LINK_WIDTH_SHIFT 0 3628a7cd276SAlex Deucher # define LC_LINK_WIDTH_MASK 0x7 3638a7cd276SAlex Deucher # define LC_LINK_WIDTH_X0 0 3648a7cd276SAlex Deucher # define LC_LINK_WIDTH_X1 1 3658a7cd276SAlex Deucher # define LC_LINK_WIDTH_X2 2 3668a7cd276SAlex Deucher # define LC_LINK_WIDTH_X4 3 3678a7cd276SAlex Deucher # define LC_LINK_WIDTH_X8 4 3688a7cd276SAlex Deucher # define LC_LINK_WIDTH_X16 6 3698a7cd276SAlex Deucher # define LC_LINK_WIDTH_RD_SHIFT 4 3708a7cd276SAlex Deucher # define LC_LINK_WIDTH_RD_MASK 0x70 3718a7cd276SAlex Deucher # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 3728a7cd276SAlex Deucher # define LC_RECONFIG_NOW (1 << 8) 3738a7cd276SAlex Deucher # define LC_RENEGOTIATION_SUPPORT (1 << 9) 3748a7cd276SAlex Deucher # define LC_RENEGOTIATE_EN (1 << 10) 3758a7cd276SAlex Deucher # define LC_SHORT_RECONFIG_EN (1 << 11) 3768a7cd276SAlex Deucher # define LC_UPCONFIGURE_SUPPORT (1 << 12) 3778a7cd276SAlex Deucher # define LC_UPCONFIGURE_DIS (1 << 13) 3788a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 3798a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 3808a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE_SHIFT 21 3817235711aSAlex Deucher #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 3827235711aSAlex Deucher # define LC_XMIT_N_FTS(x) ((x) << 0) 3837235711aSAlex Deucher # define LC_XMIT_N_FTS_MASK (0xff << 0) 3847235711aSAlex Deucher # define LC_XMIT_N_FTS_SHIFT 0 3857235711aSAlex Deucher # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 3867235711aSAlex Deucher # define LC_N_FTS_MASK (0xff << 24) 3878a7cd276SAlex Deucher #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 3888a7cd276SAlex Deucher # define LC_GEN2_EN_STRAP (1 << 0) 3898a7cd276SAlex Deucher # define LC_GEN3_EN_STRAP (1 << 1) 3908a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 3918a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 3928a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 3938a7cd276SAlex Deucher # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 3948a7cd276SAlex Deucher # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 3958a7cd276SAlex Deucher # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 3968a7cd276SAlex Deucher # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 3978a7cd276SAlex Deucher # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 3988a7cd276SAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 3998a7cd276SAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 4008a7cd276SAlex Deucher # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 4018a7cd276SAlex Deucher # define LC_CURRENT_DATA_RATE_SHIFT 13 4028a7cd276SAlex Deucher # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 4038a7cd276SAlex Deucher # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 4048a7cd276SAlex Deucher # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 4058a7cd276SAlex Deucher # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 4068a7cd276SAlex Deucher # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 4078a7cd276SAlex Deucher 4087235711aSAlex Deucher #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 4097235711aSAlex Deucher # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 4107235711aSAlex Deucher # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 4117235711aSAlex Deucher 4127235711aSAlex Deucher #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 4137235711aSAlex Deucher # define LC_GO_TO_RECOVERY (1 << 30) 4148a7cd276SAlex Deucher #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 4158a7cd276SAlex Deucher # define LC_REDO_EQ (1 << 5) 4168a7cd276SAlex Deucher # define LC_SET_QUIESCE (1 << 13) 4178a7cd276SAlex Deucher 4188a7cd276SAlex Deucher /* direct registers */ 4196e2c3c0aSAlex Deucher #define PCIE_INDEX 0x38 4206e2c3c0aSAlex Deucher #define PCIE_DATA 0x3C 4216e2c3c0aSAlex Deucher 42241a524abSAlex Deucher #define SMC_IND_INDEX_0 0x200 42341a524abSAlex Deucher #define SMC_IND_DATA_0 0x204 42441a524abSAlex Deucher 42541a524abSAlex Deucher #define SMC_IND_ACCESS_CNTL 0x240 42641a524abSAlex Deucher #define AUTO_INCREMENT_IND_0 (1 << 0) 42741a524abSAlex Deucher 42841a524abSAlex Deucher #define SMC_MESSAGE_0 0x250 42941a524abSAlex Deucher #define SMC_MSG_MASK 0xffff 43041a524abSAlex Deucher #define SMC_RESP_0 0x254 43141a524abSAlex Deucher #define SMC_RESP_MASK 0xffff 43241a524abSAlex Deucher 43341a524abSAlex Deucher #define SMC_MSG_ARG_0 0x290 43441a524abSAlex Deucher 4351c49165dSAlex Deucher #define VGA_HDP_CONTROL 0x328 4361c49165dSAlex Deucher #define VGA_MEMORY_DISABLE (1 << 4) 4371c49165dSAlex Deucher 4388cc1a532SAlex Deucher #define DMIF_ADDR_CALC 0xC00 4398cc1a532SAlex Deucher 440bc01a8c7SAlex Deucher #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 441bc01a8c7SAlex Deucher # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 442bc01a8c7SAlex Deucher # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 443bc01a8c7SAlex Deucher 4441c49165dSAlex Deucher #define SRBM_GFX_CNTL 0xE44 4451c49165dSAlex Deucher #define PIPEID(x) ((x) << 0) 4461c49165dSAlex Deucher #define MEID(x) ((x) << 2) 4471c49165dSAlex Deucher #define VMID(x) ((x) << 4) 4481c49165dSAlex Deucher #define QUEUEID(x) ((x) << 8) 4491c49165dSAlex Deucher 4506f2043ceSAlex Deucher #define SRBM_STATUS2 0xE4C 451cc066715SAlex Deucher #define SDMA_BUSY (1 << 5) 452cc066715SAlex Deucher #define SDMA1_BUSY (1 << 6) 4536f2043ceSAlex Deucher #define SRBM_STATUS 0xE50 454cc066715SAlex Deucher #define UVD_RQ_PENDING (1 << 1) 455cc066715SAlex Deucher #define GRBM_RQ_PENDING (1 << 5) 456cc066715SAlex Deucher #define VMC_BUSY (1 << 8) 457cc066715SAlex Deucher #define MCB_BUSY (1 << 9) 458cc066715SAlex Deucher #define MCB_NON_DISPLAY_BUSY (1 << 10) 459cc066715SAlex Deucher #define MCC_BUSY (1 << 11) 460cc066715SAlex Deucher #define MCD_BUSY (1 << 12) 461cc066715SAlex Deucher #define SEM_BUSY (1 << 14) 462cc066715SAlex Deucher #define IH_BUSY (1 << 17) 463cc066715SAlex Deucher #define UVD_BUSY (1 << 19) 4646f2043ceSAlex Deucher 46521a93e13SAlex Deucher #define SRBM_SOFT_RESET 0xE60 46621a93e13SAlex Deucher #define SOFT_RESET_BIF (1 << 1) 46721a93e13SAlex Deucher #define SOFT_RESET_R0PLL (1 << 4) 46821a93e13SAlex Deucher #define SOFT_RESET_DC (1 << 5) 46921a93e13SAlex Deucher #define SOFT_RESET_SDMA1 (1 << 6) 47021a93e13SAlex Deucher #define SOFT_RESET_GRBM (1 << 8) 47121a93e13SAlex Deucher #define SOFT_RESET_HDP (1 << 9) 47221a93e13SAlex Deucher #define SOFT_RESET_IH (1 << 10) 47321a93e13SAlex Deucher #define SOFT_RESET_MC (1 << 11) 47421a93e13SAlex Deucher #define SOFT_RESET_ROM (1 << 14) 47521a93e13SAlex Deucher #define SOFT_RESET_SEM (1 << 15) 47621a93e13SAlex Deucher #define SOFT_RESET_VMC (1 << 17) 47721a93e13SAlex Deucher #define SOFT_RESET_SDMA (1 << 20) 47821a93e13SAlex Deucher #define SOFT_RESET_TST (1 << 21) 47921a93e13SAlex Deucher #define SOFT_RESET_REGBB (1 << 22) 48021a93e13SAlex Deucher #define SOFT_RESET_ORB (1 << 23) 48121a93e13SAlex Deucher #define SOFT_RESET_VCE (1 << 24) 48221a93e13SAlex Deucher 483dc12a3ecSLeo Liu #define SRBM_READ_ERROR 0xE98 484dc12a3ecSLeo Liu #define SRBM_INT_CNTL 0xEA0 485dc12a3ecSLeo Liu #define SRBM_INT_ACK 0xEA8 486dc12a3ecSLeo Liu 4871c49165dSAlex Deucher #define VM_L2_CNTL 0x1400 4881c49165dSAlex Deucher #define ENABLE_L2_CACHE (1 << 0) 4891c49165dSAlex Deucher #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 4901c49165dSAlex Deucher #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 4911c49165dSAlex Deucher #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 4921c49165dSAlex Deucher #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 4931c49165dSAlex Deucher #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 4941c49165dSAlex Deucher #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 4951c49165dSAlex Deucher #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 4961c49165dSAlex Deucher #define VM_L2_CNTL2 0x1404 4971c49165dSAlex Deucher #define INVALIDATE_ALL_L1_TLBS (1 << 0) 4981c49165dSAlex Deucher #define INVALIDATE_L2_CACHE (1 << 1) 4991c49165dSAlex Deucher #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 5001c49165dSAlex Deucher #define INVALIDATE_PTE_AND_PDE_CACHES 0 5011c49165dSAlex Deucher #define INVALIDATE_ONLY_PTE_CACHES 1 5021c49165dSAlex Deucher #define INVALIDATE_ONLY_PDE_CACHES 2 5031c49165dSAlex Deucher #define VM_L2_CNTL3 0x1408 5041c49165dSAlex Deucher #define BANK_SELECT(x) ((x) << 0) 5051c49165dSAlex Deucher #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 5061c49165dSAlex Deucher #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 5071c49165dSAlex Deucher #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 5081c49165dSAlex Deucher #define VM_L2_STATUS 0x140C 5091c49165dSAlex Deucher #define L2_BUSY (1 << 0) 5101c49165dSAlex Deucher #define VM_CONTEXT0_CNTL 0x1410 5111c49165dSAlex Deucher #define ENABLE_CONTEXT (1 << 0) 5121c49165dSAlex Deucher #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 513a00024b0SAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 5141c49165dSAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 515a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 516a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 517a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 518a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 519a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 520a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 521a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 522a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 523a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 524a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 5251c89d27fSChristian König #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 5261c49165dSAlex Deucher #define VM_CONTEXT1_CNTL 0x1414 5271c49165dSAlex Deucher #define VM_CONTEXT0_CNTL2 0x1430 5281c49165dSAlex Deucher #define VM_CONTEXT1_CNTL2 0x1434 5291c49165dSAlex Deucher #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 5301c49165dSAlex Deucher #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 5311c49165dSAlex Deucher #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 5321c49165dSAlex Deucher #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 5331c49165dSAlex Deucher #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 5341c49165dSAlex Deucher #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 5351c49165dSAlex Deucher #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 5361c49165dSAlex Deucher #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 5371c49165dSAlex Deucher 5381c49165dSAlex Deucher #define VM_INVALIDATE_REQUEST 0x1478 5391c49165dSAlex Deucher #define VM_INVALIDATE_RESPONSE 0x147c 5401c49165dSAlex Deucher 5419d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 5423ec7d11bSAlex Deucher #define PROTECTIONS_MASK (0xf << 0) 5433ec7d11bSAlex Deucher #define PROTECTIONS_SHIFT 0 5443ec7d11bSAlex Deucher /* bit 0: range 5453ec7d11bSAlex Deucher * bit 1: pde0 5463ec7d11bSAlex Deucher * bit 2: valid 5473ec7d11bSAlex Deucher * bit 3: read 5483ec7d11bSAlex Deucher * bit 4: write 5493ec7d11bSAlex Deucher */ 5503ec7d11bSAlex Deucher #define MEMORY_CLIENT_ID_MASK (0xff << 12) 551939c0d3cSAlex Deucher #define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12) 5523ec7d11bSAlex Deucher #define MEMORY_CLIENT_ID_SHIFT 12 5533ec7d11bSAlex Deucher #define MEMORY_CLIENT_RW_MASK (1 << 24) 5543ec7d11bSAlex Deucher #define MEMORY_CLIENT_RW_SHIFT 24 5553ec7d11bSAlex Deucher #define FAULT_VMID_MASK (0xf << 25) 5563ec7d11bSAlex Deucher #define FAULT_VMID_SHIFT 25 5573ec7d11bSAlex Deucher 5583ec7d11bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 5599d97c99bSAlex Deucher 5609d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 5619d97c99bSAlex Deucher 5621c49165dSAlex Deucher #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 5631c49165dSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 5641c49165dSAlex Deucher 5651c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 5661c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 5671c49165dSAlex Deucher #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 5681c49165dSAlex Deucher #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 5691c49165dSAlex Deucher #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 5701c49165dSAlex Deucher #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 5711c49165dSAlex Deucher #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 5721c49165dSAlex Deucher #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 5731c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 5741c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 5751c49165dSAlex Deucher 5761c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 5771c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 5781c49165dSAlex Deucher 57922c775ceSAlex Deucher #define VM_L2_CG 0x15c0 58022c775ceSAlex Deucher #define MC_CG_ENABLE (1 << 18) 58122c775ceSAlex Deucher #define MC_LS_ENABLE (1 << 19) 58222c775ceSAlex Deucher 5838cc1a532SAlex Deucher #define MC_SHARED_CHMAP 0x2004 5848cc1a532SAlex Deucher #define NOOFCHAN_SHIFT 12 5858cc1a532SAlex Deucher #define NOOFCHAN_MASK 0x0000f000 5868cc1a532SAlex Deucher #define MC_SHARED_CHREMAP 0x2008 5878cc1a532SAlex Deucher 5881c49165dSAlex Deucher #define CHUB_CONTROL 0x1864 5891c49165dSAlex Deucher #define BYPASS_VM (1 << 0) 5901c49165dSAlex Deucher 5911c49165dSAlex Deucher #define MC_VM_FB_LOCATION 0x2024 5921c49165dSAlex Deucher #define MC_VM_AGP_TOP 0x2028 5931c49165dSAlex Deucher #define MC_VM_AGP_BOT 0x202C 5941c49165dSAlex Deucher #define MC_VM_AGP_BASE 0x2030 5951c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 5961c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 5971c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 5981c49165dSAlex Deucher 5991c49165dSAlex Deucher #define MC_VM_MX_L1_TLB_CNTL 0x2064 6001c49165dSAlex Deucher #define ENABLE_L1_TLB (1 << 0) 6011c49165dSAlex Deucher #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 6021c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 6031c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 6041c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 6051c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 6061c49165dSAlex Deucher #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 6071c49165dSAlex Deucher #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 6081c49165dSAlex Deucher #define MC_VM_FB_OFFSET 0x2068 6091c49165dSAlex Deucher 610bc8273feSAlex Deucher #define MC_SHARED_BLACKOUT_CNTL 0x20ac 611bc8273feSAlex Deucher 61222c775ceSAlex Deucher #define MC_HUB_MISC_HUB_CG 0x20b8 61322c775ceSAlex Deucher #define MC_HUB_MISC_VM_CG 0x20bc 61422c775ceSAlex Deucher 61522c775ceSAlex Deucher #define MC_HUB_MISC_SIP_CG 0x20c0 61622c775ceSAlex Deucher 61722c775ceSAlex Deucher #define MC_XPB_CLK_GAT 0x2478 61822c775ceSAlex Deucher 61922c775ceSAlex Deucher #define MC_CITF_MISC_RD_CG 0x2648 62022c775ceSAlex Deucher #define MC_CITF_MISC_WR_CG 0x264c 62122c775ceSAlex Deucher #define MC_CITF_MISC_VM_CG 0x2650 62222c775ceSAlex Deucher 6238cc1a532SAlex Deucher #define MC_ARB_RAMCFG 0x2760 6248cc1a532SAlex Deucher #define NOOFBANK_SHIFT 0 6258cc1a532SAlex Deucher #define NOOFBANK_MASK 0x00000003 6268cc1a532SAlex Deucher #define NOOFRANK_SHIFT 2 6278cc1a532SAlex Deucher #define NOOFRANK_MASK 0x00000004 6288cc1a532SAlex Deucher #define NOOFROWS_SHIFT 3 6298cc1a532SAlex Deucher #define NOOFROWS_MASK 0x00000038 6308cc1a532SAlex Deucher #define NOOFCOLS_SHIFT 6 6318cc1a532SAlex Deucher #define NOOFCOLS_MASK 0x000000C0 6328cc1a532SAlex Deucher #define CHANSIZE_SHIFT 8 6338cc1a532SAlex Deucher #define CHANSIZE_MASK 0x00000100 6348cc1a532SAlex Deucher #define NOOFGROUPS_SHIFT 12 6358cc1a532SAlex Deucher #define NOOFGROUPS_MASK 0x00001000 6368cc1a532SAlex Deucher 637cc8dbbb4SAlex Deucher #define MC_ARB_DRAM_TIMING 0x2774 638cc8dbbb4SAlex Deucher #define MC_ARB_DRAM_TIMING2 0x2778 639cc8dbbb4SAlex Deucher 640cc8dbbb4SAlex Deucher #define MC_ARB_BURST_TIME 0x2808 641cc8dbbb4SAlex Deucher #define STATE0(x) ((x) << 0) 642cc8dbbb4SAlex Deucher #define STATE0_MASK (0x1f << 0) 643cc8dbbb4SAlex Deucher #define STATE0_SHIFT 0 644cc8dbbb4SAlex Deucher #define STATE1(x) ((x) << 5) 645cc8dbbb4SAlex Deucher #define STATE1_MASK (0x1f << 5) 646cc8dbbb4SAlex Deucher #define STATE1_SHIFT 5 647cc8dbbb4SAlex Deucher #define STATE2(x) ((x) << 10) 648cc8dbbb4SAlex Deucher #define STATE2_MASK (0x1f << 10) 649cc8dbbb4SAlex Deucher #define STATE2_SHIFT 10 650cc8dbbb4SAlex Deucher #define STATE3(x) ((x) << 15) 651cc8dbbb4SAlex Deucher #define STATE3_MASK (0x1f << 15) 652cc8dbbb4SAlex Deucher #define STATE3_SHIFT 15 653cc8dbbb4SAlex Deucher 654cc8dbbb4SAlex Deucher #define MC_SEQ_RAS_TIMING 0x28a0 655cc8dbbb4SAlex Deucher #define MC_SEQ_CAS_TIMING 0x28a4 656cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING 0x28a8 657cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING2 0x28ac 658cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_TIMING 0x28b0 659cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D0 0x28b4 660cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D1 0x28b8 661cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D0 0x28bc 662cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D1 0x28c0 663cc8dbbb4SAlex Deucher 664bc8273feSAlex Deucher #define MC_SEQ_SUP_CNTL 0x28c8 665bc8273feSAlex Deucher #define RUN_MASK (1 << 0) 666bc8273feSAlex Deucher #define MC_SEQ_SUP_PGM 0x28cc 667cc8dbbb4SAlex Deucher #define MC_PMG_AUTO_CMD 0x28d0 668bc8273feSAlex Deucher 669bc8273feSAlex Deucher #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 670bc8273feSAlex Deucher #define TRAIN_DONE_D0 (1 << 30) 671bc8273feSAlex Deucher #define TRAIN_DONE_D1 (1 << 31) 672bc8273feSAlex Deucher 673bc8273feSAlex Deucher #define MC_IO_PAD_CNTL_D0 0x29d0 674bc8273feSAlex Deucher #define MEM_FALL_OUT_CMD (1 << 8) 675bc8273feSAlex Deucher 676cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0 0x2a00 677cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 678cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 679cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_VALUE 3 680cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_SHIFT 12 681cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 682cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_VALUE 1 683cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_SHIFT 28 684cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 685cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_VALUE 5 686cc8dbbb4SAlex Deucher #define MC_SEQ_MISC1 0x2a04 687cc8dbbb4SAlex Deucher #define MC_SEQ_RESERVE_M 0x2a08 688cc8dbbb4SAlex Deucher #define MC_PMG_CMD_EMRS 0x2a0c 689cc8dbbb4SAlex Deucher 690bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 691bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_DATA 0x2a48 692bc8273feSAlex Deucher 693cc8dbbb4SAlex Deucher #define MC_SEQ_MISC5 0x2a54 694cc8dbbb4SAlex Deucher #define MC_SEQ_MISC6 0x2a58 695cc8dbbb4SAlex Deucher 696cc8dbbb4SAlex Deucher #define MC_SEQ_MISC7 0x2a64 697cc8dbbb4SAlex Deucher 698cc8dbbb4SAlex Deucher #define MC_SEQ_RAS_TIMING_LP 0x2a6c 699cc8dbbb4SAlex Deucher #define MC_SEQ_CAS_TIMING_LP 0x2a70 700cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING_LP 0x2a74 701cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING2_LP 0x2a78 702cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 703cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D1_LP 0x2a80 704cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 705cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 706cc8dbbb4SAlex Deucher 707cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS 0x2aac 708cc8dbbb4SAlex Deucher 709cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 710cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D1_LP 0x2b20 711cc8dbbb4SAlex Deucher 712cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS1 0x2b44 713cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 714cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_TIMING_LP 0x2b4c 715cc8dbbb4SAlex Deucher 716cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_2 0x2b54 717cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_2_LP 0x2b58 718cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS2 0x2b5c 719cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 720cc8dbbb4SAlex Deucher 721cc8dbbb4SAlex Deucher #define MCLK_PWRMGT_CNTL 0x2ba0 722cc8dbbb4SAlex Deucher # define DLL_SPEED(x) ((x) << 0) 723cc8dbbb4SAlex Deucher # define DLL_SPEED_MASK (0x1f << 0) 724cc8dbbb4SAlex Deucher # define DLL_READY (1 << 6) 725cc8dbbb4SAlex Deucher # define MC_INT_CNTL (1 << 7) 726cc8dbbb4SAlex Deucher # define MRDCK0_PDNB (1 << 8) 727cc8dbbb4SAlex Deucher # define MRDCK1_PDNB (1 << 9) 728cc8dbbb4SAlex Deucher # define MRDCK0_RESET (1 << 16) 729cc8dbbb4SAlex Deucher # define MRDCK1_RESET (1 << 17) 730cc8dbbb4SAlex Deucher # define DLL_READY_READ (1 << 24) 731cc8dbbb4SAlex Deucher #define DLL_CNTL 0x2ba4 732cc8dbbb4SAlex Deucher # define MRDCK0_BYPASS (1 << 24) 733cc8dbbb4SAlex Deucher # define MRDCK1_BYPASS (1 << 25) 734cc8dbbb4SAlex Deucher 735cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL 0x2bb4 736cc8dbbb4SAlex Deucher #define BWCTRL(x) ((x) << 20) 737cc8dbbb4SAlex Deucher #define BWCTRL_MASK (0xff << 20) 738cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL_1 0x2bb8 739cc8dbbb4SAlex Deucher #define VCO_MODE(x) ((x) << 0) 740cc8dbbb4SAlex Deucher #define VCO_MODE_MASK (3 << 0) 741cc8dbbb4SAlex Deucher #define CLKFRAC(x) ((x) << 4) 742cc8dbbb4SAlex Deucher #define CLKFRAC_MASK (0xfff << 4) 743cc8dbbb4SAlex Deucher #define CLKF(x) ((x) << 16) 744cc8dbbb4SAlex Deucher #define CLKF_MASK (0xfff << 16) 745cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL_2 0x2bbc 746cc8dbbb4SAlex Deucher #define MPLL_AD_FUNC_CNTL 0x2bc0 747cc8dbbb4SAlex Deucher #define YCLK_POST_DIV(x) ((x) << 0) 748cc8dbbb4SAlex Deucher #define YCLK_POST_DIV_MASK (7 << 0) 749cc8dbbb4SAlex Deucher #define MPLL_DQ_FUNC_CNTL 0x2bc4 750cc8dbbb4SAlex Deucher #define YCLK_SEL(x) ((x) << 4) 751cc8dbbb4SAlex Deucher #define YCLK_SEL_MASK (1 << 4) 752cc8dbbb4SAlex Deucher 753cc8dbbb4SAlex Deucher #define MPLL_SS1 0x2bcc 754cc8dbbb4SAlex Deucher #define CLKV(x) ((x) << 0) 755cc8dbbb4SAlex Deucher #define CLKV_MASK (0x3ffffff << 0) 756cc8dbbb4SAlex Deucher #define MPLL_SS2 0x2bd0 757cc8dbbb4SAlex Deucher #define CLKS(x) ((x) << 0) 758cc8dbbb4SAlex Deucher #define CLKS_MASK (0xfff << 0) 759cc8dbbb4SAlex Deucher 7608cc1a532SAlex Deucher #define HDP_HOST_PATH_CNTL 0x2C00 76122c775ceSAlex Deucher #define CLOCK_GATING_DIS (1 << 23) 7628cc1a532SAlex Deucher #define HDP_NONSURFACE_BASE 0x2C04 7638cc1a532SAlex Deucher #define HDP_NONSURFACE_INFO 0x2C08 7648cc1a532SAlex Deucher #define HDP_NONSURFACE_SIZE 0x2C0C 7658cc1a532SAlex Deucher 7668cc1a532SAlex Deucher #define HDP_ADDR_CONFIG 0x2F48 7678cc1a532SAlex Deucher #define HDP_MISC_CNTL 0x2F4C 7688cc1a532SAlex Deucher #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 76922c775ceSAlex Deucher #define HDP_MEM_POWER_LS 0x2F50 77022c775ceSAlex Deucher #define HDP_LS_ENABLE (1 << 0) 77122c775ceSAlex Deucher 77222c775ceSAlex Deucher #define ATC_MISC_CG 0x3350 7738cc1a532SAlex Deucher 7740279ed19SAlex Deucher #define GMCON_RENG_EXECUTE 0x3508 7750279ed19SAlex Deucher #define RENG_EXECUTE_ON_PWR_UP (1 << 0) 7760279ed19SAlex Deucher #define GMCON_MISC 0x350c 7770279ed19SAlex Deucher #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11) 7780279ed19SAlex Deucher #define STCTRL_STUTTER_EN (1 << 16) 7790279ed19SAlex Deucher 7800279ed19SAlex Deucher #define GMCON_PGFSM_CONFIG 0x3538 7810279ed19SAlex Deucher #define GMCON_PGFSM_WRITE 0x353c 7820279ed19SAlex Deucher #define GMCON_PGFSM_READ 0x3540 7830279ed19SAlex Deucher #define GMCON_MISC3 0x3544 7840279ed19SAlex Deucher 785cc8dbbb4SAlex Deucher #define MC_SEQ_CNTL_3 0x3600 786cc8dbbb4SAlex Deucher # define CAC_EN (1 << 31) 787cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CTRL 0x3604 788cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CTRL_LP 0x3608 789cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD0 0x360c 790cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD0_LP 0x3610 791cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD1 0x3614 792cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD1_LP 0x3618 793cc8dbbb4SAlex Deucher 794cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CTL 0x3628 795cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 796cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CMD 0x3630 797cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 798cc8dbbb4SAlex Deucher #define MC_SEQ_DLL_STBY 0x3638 799cc8dbbb4SAlex Deucher #define MC_SEQ_DLL_STBY_LP 0x363c 800cc8dbbb4SAlex Deucher 801a59781bbSAlex Deucher #define IH_RB_CNTL 0x3e00 802a59781bbSAlex Deucher # define IH_RB_ENABLE (1 << 0) 803a59781bbSAlex Deucher # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 804a59781bbSAlex Deucher # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 805a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 806a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 807a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 808a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 809a59781bbSAlex Deucher #define IH_RB_BASE 0x3e04 810a59781bbSAlex Deucher #define IH_RB_RPTR 0x3e08 811a59781bbSAlex Deucher #define IH_RB_WPTR 0x3e0c 812a59781bbSAlex Deucher # define RB_OVERFLOW (1 << 0) 813a59781bbSAlex Deucher # define WPTR_OFFSET_MASK 0x3fffc 814a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_HI 0x3e10 815a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_LO 0x3e14 816a59781bbSAlex Deucher #define IH_CNTL 0x3e18 817a59781bbSAlex Deucher # define ENABLE_INTR (1 << 0) 818a59781bbSAlex Deucher # define IH_MC_SWAP(x) ((x) << 1) 819a59781bbSAlex Deucher # define IH_MC_SWAP_NONE 0 820a59781bbSAlex Deucher # define IH_MC_SWAP_16BIT 1 821a59781bbSAlex Deucher # define IH_MC_SWAP_32BIT 2 822a59781bbSAlex Deucher # define IH_MC_SWAP_64BIT 3 823a59781bbSAlex Deucher # define RPTR_REARM (1 << 4) 824a59781bbSAlex Deucher # define MC_WRREQ_CREDIT(x) ((x) << 15) 825a59781bbSAlex Deucher # define MC_WR_CLEAN_CNT(x) ((x) << 20) 826a59781bbSAlex Deucher # define MC_VMID(x) ((x) << 25) 827a59781bbSAlex Deucher 828cc8dbbb4SAlex Deucher #define BIF_LNCNT_RESET 0x5220 829cc8dbbb4SAlex Deucher # define RESET_LNCNT_EN (1 << 0) 830cc8dbbb4SAlex Deucher 8311c49165dSAlex Deucher #define CONFIG_MEMSIZE 0x5428 8321c49165dSAlex Deucher 833a59781bbSAlex Deucher #define INTERRUPT_CNTL 0x5468 834a59781bbSAlex Deucher # define IH_DUMMY_RD_OVERRIDE (1 << 0) 835a59781bbSAlex Deucher # define IH_DUMMY_RD_EN (1 << 1) 836a59781bbSAlex Deucher # define IH_REQ_NONSNOOP_EN (1 << 3) 837a59781bbSAlex Deucher # define GEN_IH_INT_EN (1 << 8) 838a59781bbSAlex Deucher #define INTERRUPT_CNTL2 0x546c 839a59781bbSAlex Deucher 8401c49165dSAlex Deucher #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 8411c49165dSAlex Deucher 8428cc1a532SAlex Deucher #define BIF_FB_EN 0x5490 8438cc1a532SAlex Deucher #define FB_READ_EN (1 << 0) 8448cc1a532SAlex Deucher #define FB_WRITE_EN (1 << 1) 8458cc1a532SAlex Deucher 8461c49165dSAlex Deucher #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 8471c49165dSAlex Deucher 8482cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_REQ 0x54DC 8492cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_DONE 0x54E0 8502cae3bc3SAlex Deucher #define CP0 (1 << 0) 8512cae3bc3SAlex Deucher #define CP1 (1 << 1) 8522cae3bc3SAlex Deucher #define CP2 (1 << 2) 8532cae3bc3SAlex Deucher #define CP3 (1 << 3) 8542cae3bc3SAlex Deucher #define CP4 (1 << 4) 8552cae3bc3SAlex Deucher #define CP5 (1 << 5) 8562cae3bc3SAlex Deucher #define CP6 (1 << 6) 8572cae3bc3SAlex Deucher #define CP7 (1 << 7) 8582cae3bc3SAlex Deucher #define CP8 (1 << 8) 8592cae3bc3SAlex Deucher #define CP9 (1 << 9) 8602cae3bc3SAlex Deucher #define SDMA0 (1 << 10) 8612cae3bc3SAlex Deucher #define SDMA1 (1 << 11) 8622cae3bc3SAlex Deucher 863cd84a27dSAlex Deucher /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 864cd84a27dSAlex Deucher #define LB_MEMORY_CTRL 0x6b04 865cd84a27dSAlex Deucher #define LB_MEMORY_SIZE(x) ((x) << 0) 866cd84a27dSAlex Deucher #define LB_MEMORY_CONFIG(x) ((x) << 20) 867cd84a27dSAlex Deucher 868cd84a27dSAlex Deucher #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 869cd84a27dSAlex Deucher # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 870cd84a27dSAlex Deucher #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 871cd84a27dSAlex Deucher # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 872cd84a27dSAlex Deucher # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 873cd84a27dSAlex Deucher 874a59781bbSAlex Deucher /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 875a59781bbSAlex Deucher #define LB_VLINE_STATUS 0x6b24 876a59781bbSAlex Deucher # define VLINE_OCCURRED (1 << 0) 877a59781bbSAlex Deucher # define VLINE_ACK (1 << 4) 878a59781bbSAlex Deucher # define VLINE_STAT (1 << 12) 879a59781bbSAlex Deucher # define VLINE_INTERRUPT (1 << 16) 880a59781bbSAlex Deucher # define VLINE_INTERRUPT_TYPE (1 << 17) 881a59781bbSAlex Deucher /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 882a59781bbSAlex Deucher #define LB_VBLANK_STATUS 0x6b2c 883a59781bbSAlex Deucher # define VBLANK_OCCURRED (1 << 0) 884a59781bbSAlex Deucher # define VBLANK_ACK (1 << 4) 885a59781bbSAlex Deucher # define VBLANK_STAT (1 << 12) 886a59781bbSAlex Deucher # define VBLANK_INTERRUPT (1 << 16) 887a59781bbSAlex Deucher # define VBLANK_INTERRUPT_TYPE (1 << 17) 888a59781bbSAlex Deucher 889a59781bbSAlex Deucher /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 890a59781bbSAlex Deucher #define LB_INTERRUPT_MASK 0x6b20 891a59781bbSAlex Deucher # define VBLANK_INTERRUPT_MASK (1 << 0) 892a59781bbSAlex Deucher # define VLINE_INTERRUPT_MASK (1 << 4) 893a59781bbSAlex Deucher # define VLINE2_INTERRUPT_MASK (1 << 8) 894a59781bbSAlex Deucher 895a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS 0x60f4 896a59781bbSAlex Deucher # define LB_D1_VLINE_INTERRUPT (1 << 2) 897a59781bbSAlex Deucher # define LB_D1_VBLANK_INTERRUPT (1 << 3) 898a59781bbSAlex Deucher # define DC_HPD1_INTERRUPT (1 << 17) 899a59781bbSAlex Deucher # define DC_HPD1_RX_INTERRUPT (1 << 18) 900a59781bbSAlex Deucher # define DACA_AUTODETECT_INTERRUPT (1 << 22) 901a59781bbSAlex Deucher # define DACB_AUTODETECT_INTERRUPT (1 << 23) 902a59781bbSAlex Deucher # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 903a59781bbSAlex Deucher # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 904a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 905a59781bbSAlex Deucher # define LB_D2_VLINE_INTERRUPT (1 << 2) 906a59781bbSAlex Deucher # define LB_D2_VBLANK_INTERRUPT (1 << 3) 907a59781bbSAlex Deucher # define DC_HPD2_INTERRUPT (1 << 17) 908a59781bbSAlex Deucher # define DC_HPD2_RX_INTERRUPT (1 << 18) 909a59781bbSAlex Deucher # define DISP_TIMER_INTERRUPT (1 << 24) 910a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 911a59781bbSAlex Deucher # define LB_D3_VLINE_INTERRUPT (1 << 2) 912a59781bbSAlex Deucher # define LB_D3_VBLANK_INTERRUPT (1 << 3) 913a59781bbSAlex Deucher # define DC_HPD3_INTERRUPT (1 << 17) 914a59781bbSAlex Deucher # define DC_HPD3_RX_INTERRUPT (1 << 18) 915a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 916a59781bbSAlex Deucher # define LB_D4_VLINE_INTERRUPT (1 << 2) 917a59781bbSAlex Deucher # define LB_D4_VBLANK_INTERRUPT (1 << 3) 918a59781bbSAlex Deucher # define DC_HPD4_INTERRUPT (1 << 17) 919a59781bbSAlex Deucher # define DC_HPD4_RX_INTERRUPT (1 << 18) 920a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 921a59781bbSAlex Deucher # define LB_D5_VLINE_INTERRUPT (1 << 2) 922a59781bbSAlex Deucher # define LB_D5_VBLANK_INTERRUPT (1 << 3) 923a59781bbSAlex Deucher # define DC_HPD5_INTERRUPT (1 << 17) 924a59781bbSAlex Deucher # define DC_HPD5_RX_INTERRUPT (1 << 18) 925a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 926a59781bbSAlex Deucher # define LB_D6_VLINE_INTERRUPT (1 << 2) 927a59781bbSAlex Deucher # define LB_D6_VBLANK_INTERRUPT (1 << 3) 928a59781bbSAlex Deucher # define DC_HPD6_INTERRUPT (1 << 17) 929a59781bbSAlex Deucher # define DC_HPD6_RX_INTERRUPT (1 << 18) 930a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 931a59781bbSAlex Deucher 932f5d636d2SChristian König /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 933f5d636d2SChristian König #define GRPH_INT_STATUS 0x6858 934f5d636d2SChristian König # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 935f5d636d2SChristian König # define GRPH_PFLIP_INT_CLEAR (1 << 8) 936f5d636d2SChristian König /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 937f5d636d2SChristian König #define GRPH_INT_CONTROL 0x685c 938f5d636d2SChristian König # define GRPH_PFLIP_INT_MASK (1 << 0) 939f5d636d2SChristian König # define GRPH_PFLIP_INT_TYPE (1 << 8) 940f5d636d2SChristian König 941a59781bbSAlex Deucher #define DAC_AUTODETECT_INT_CONTROL 0x67c8 942a59781bbSAlex Deucher 943a59781bbSAlex Deucher #define DC_HPD1_INT_STATUS 0x601c 944a59781bbSAlex Deucher #define DC_HPD2_INT_STATUS 0x6028 945a59781bbSAlex Deucher #define DC_HPD3_INT_STATUS 0x6034 946a59781bbSAlex Deucher #define DC_HPD4_INT_STATUS 0x6040 947a59781bbSAlex Deucher #define DC_HPD5_INT_STATUS 0x604c 948a59781bbSAlex Deucher #define DC_HPD6_INT_STATUS 0x6058 949a59781bbSAlex Deucher # define DC_HPDx_INT_STATUS (1 << 0) 950a59781bbSAlex Deucher # define DC_HPDx_SENSE (1 << 1) 951a59781bbSAlex Deucher # define DC_HPDx_SENSE_DELAYED (1 << 4) 952a59781bbSAlex Deucher # define DC_HPDx_RX_INT_STATUS (1 << 8) 953a59781bbSAlex Deucher 954a59781bbSAlex Deucher #define DC_HPD1_INT_CONTROL 0x6020 955a59781bbSAlex Deucher #define DC_HPD2_INT_CONTROL 0x602c 956a59781bbSAlex Deucher #define DC_HPD3_INT_CONTROL 0x6038 957a59781bbSAlex Deucher #define DC_HPD4_INT_CONTROL 0x6044 958a59781bbSAlex Deucher #define DC_HPD5_INT_CONTROL 0x6050 959a59781bbSAlex Deucher #define DC_HPD6_INT_CONTROL 0x605c 960a59781bbSAlex Deucher # define DC_HPDx_INT_ACK (1 << 0) 961a59781bbSAlex Deucher # define DC_HPDx_INT_POLARITY (1 << 8) 962a59781bbSAlex Deucher # define DC_HPDx_INT_EN (1 << 16) 963a59781bbSAlex Deucher # define DC_HPDx_RX_INT_ACK (1 << 20) 964a59781bbSAlex Deucher # define DC_HPDx_RX_INT_EN (1 << 24) 965a59781bbSAlex Deucher 966a59781bbSAlex Deucher #define DC_HPD1_CONTROL 0x6024 967a59781bbSAlex Deucher #define DC_HPD2_CONTROL 0x6030 968a59781bbSAlex Deucher #define DC_HPD3_CONTROL 0x603c 969a59781bbSAlex Deucher #define DC_HPD4_CONTROL 0x6048 970a59781bbSAlex Deucher #define DC_HPD5_CONTROL 0x6054 971a59781bbSAlex Deucher #define DC_HPD6_CONTROL 0x6060 972a59781bbSAlex Deucher # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 973a59781bbSAlex Deucher # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 974a59781bbSAlex Deucher # define DC_HPDx_EN (1 << 28) 975a59781bbSAlex Deucher 976cc8dbbb4SAlex Deucher #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 977cc8dbbb4SAlex Deucher # define STUTTER_ENABLE (1 << 0) 978cc8dbbb4SAlex Deucher 979134b480fSAlex Deucher /* DCE8 FMT blocks */ 980134b480fSAlex Deucher #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 981134b480fSAlex Deucher # define FMT_DYNAMIC_EXP_EN (1 << 0) 982134b480fSAlex Deucher # define FMT_DYNAMIC_EXP_MODE (1 << 4) 983134b480fSAlex Deucher /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 984134b480fSAlex Deucher #define FMT_CONTROL 0x6fb8 985134b480fSAlex Deucher # define FMT_PIXEL_ENCODING (1 << 16) 986134b480fSAlex Deucher /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 987134b480fSAlex Deucher #define FMT_BIT_DEPTH_CONTROL 0x6fc8 988134b480fSAlex Deucher # define FMT_TRUNCATE_EN (1 << 0) 989134b480fSAlex Deucher # define FMT_TRUNCATE_MODE (1 << 1) 990134b480fSAlex Deucher # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 991134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_EN (1 << 8) 992134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 993134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 994134b480fSAlex Deucher # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 995134b480fSAlex Deucher # define FMT_RGB_RANDOM_ENABLE (1 << 14) 996134b480fSAlex Deucher # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 997134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_EN (1 << 16) 998134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 999134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1000134b480fSAlex Deucher # define FMT_TEMPORAL_LEVEL (1 << 24) 1001134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1002134b480fSAlex Deucher # define FMT_25FRC_SEL(x) ((x) << 26) 1003134b480fSAlex Deucher # define FMT_50FRC_SEL(x) ((x) << 28) 1004134b480fSAlex Deucher # define FMT_75FRC_SEL(x) ((x) << 30) 1005134b480fSAlex Deucher #define FMT_CLAMP_CONTROL 0x6fe4 1006134b480fSAlex Deucher # define FMT_CLAMP_DATA_EN (1 << 0) 1007134b480fSAlex Deucher # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1008134b480fSAlex Deucher # define FMT_CLAMP_6BPC 0 1009134b480fSAlex Deucher # define FMT_CLAMP_8BPC 1 1010134b480fSAlex Deucher # define FMT_CLAMP_10BPC 2 1011134b480fSAlex Deucher 10128cc1a532SAlex Deucher #define GRBM_CNTL 0x8000 10138cc1a532SAlex Deucher #define GRBM_READ_TIMEOUT(x) ((x) << 0) 10148cc1a532SAlex Deucher 10156f2043ceSAlex Deucher #define GRBM_STATUS2 0x8008 10166f2043ceSAlex Deucher #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 10176f2043ceSAlex Deucher #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 10186f2043ceSAlex Deucher #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 10196f2043ceSAlex Deucher #define ME1PIPE0_RQ_PENDING (1 << 6) 10206f2043ceSAlex Deucher #define ME1PIPE1_RQ_PENDING (1 << 7) 10216f2043ceSAlex Deucher #define ME1PIPE2_RQ_PENDING (1 << 8) 10226f2043ceSAlex Deucher #define ME1PIPE3_RQ_PENDING (1 << 9) 10236f2043ceSAlex Deucher #define ME2PIPE0_RQ_PENDING (1 << 10) 10246f2043ceSAlex Deucher #define ME2PIPE1_RQ_PENDING (1 << 11) 10256f2043ceSAlex Deucher #define ME2PIPE2_RQ_PENDING (1 << 12) 10266f2043ceSAlex Deucher #define ME2PIPE3_RQ_PENDING (1 << 13) 10276f2043ceSAlex Deucher #define RLC_RQ_PENDING (1 << 14) 10286f2043ceSAlex Deucher #define RLC_BUSY (1 << 24) 10296f2043ceSAlex Deucher #define TC_BUSY (1 << 25) 10306f2043ceSAlex Deucher #define CPF_BUSY (1 << 28) 10316f2043ceSAlex Deucher #define CPC_BUSY (1 << 29) 10326f2043ceSAlex Deucher #define CPG_BUSY (1 << 30) 10336f2043ceSAlex Deucher 10346f2043ceSAlex Deucher #define GRBM_STATUS 0x8010 10356f2043ceSAlex Deucher #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 10366f2043ceSAlex Deucher #define SRBM_RQ_PENDING (1 << 5) 10376f2043ceSAlex Deucher #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 10386f2043ceSAlex Deucher #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 10396f2043ceSAlex Deucher #define GDS_DMA_RQ_PENDING (1 << 9) 10406f2043ceSAlex Deucher #define DB_CLEAN (1 << 12) 10416f2043ceSAlex Deucher #define CB_CLEAN (1 << 13) 10426f2043ceSAlex Deucher #define TA_BUSY (1 << 14) 10436f2043ceSAlex Deucher #define GDS_BUSY (1 << 15) 10446f2043ceSAlex Deucher #define WD_BUSY_NO_DMA (1 << 16) 10456f2043ceSAlex Deucher #define VGT_BUSY (1 << 17) 10466f2043ceSAlex Deucher #define IA_BUSY_NO_DMA (1 << 18) 10476f2043ceSAlex Deucher #define IA_BUSY (1 << 19) 10486f2043ceSAlex Deucher #define SX_BUSY (1 << 20) 10496f2043ceSAlex Deucher #define WD_BUSY (1 << 21) 10506f2043ceSAlex Deucher #define SPI_BUSY (1 << 22) 10516f2043ceSAlex Deucher #define BCI_BUSY (1 << 23) 10526f2043ceSAlex Deucher #define SC_BUSY (1 << 24) 10536f2043ceSAlex Deucher #define PA_BUSY (1 << 25) 10546f2043ceSAlex Deucher #define DB_BUSY (1 << 26) 10556f2043ceSAlex Deucher #define CP_COHERENCY_BUSY (1 << 28) 10566f2043ceSAlex Deucher #define CP_BUSY (1 << 29) 10576f2043ceSAlex Deucher #define CB_BUSY (1 << 30) 10586f2043ceSAlex Deucher #define GUI_ACTIVE (1 << 31) 10596f2043ceSAlex Deucher #define GRBM_STATUS_SE0 0x8014 10606f2043ceSAlex Deucher #define GRBM_STATUS_SE1 0x8018 10616f2043ceSAlex Deucher #define GRBM_STATUS_SE2 0x8038 10626f2043ceSAlex Deucher #define GRBM_STATUS_SE3 0x803C 10636f2043ceSAlex Deucher #define SE_DB_CLEAN (1 << 1) 10646f2043ceSAlex Deucher #define SE_CB_CLEAN (1 << 2) 10656f2043ceSAlex Deucher #define SE_BCI_BUSY (1 << 22) 10666f2043ceSAlex Deucher #define SE_VGT_BUSY (1 << 23) 10676f2043ceSAlex Deucher #define SE_PA_BUSY (1 << 24) 10686f2043ceSAlex Deucher #define SE_TA_BUSY (1 << 25) 10696f2043ceSAlex Deucher #define SE_SX_BUSY (1 << 26) 10706f2043ceSAlex Deucher #define SE_SPI_BUSY (1 << 27) 10716f2043ceSAlex Deucher #define SE_SC_BUSY (1 << 29) 10726f2043ceSAlex Deucher #define SE_DB_BUSY (1 << 30) 10736f2043ceSAlex Deucher #define SE_CB_BUSY (1 << 31) 10746f2043ceSAlex Deucher 10756f2043ceSAlex Deucher #define GRBM_SOFT_RESET 0x8020 10766f2043ceSAlex Deucher #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 10776f2043ceSAlex Deucher #define SOFT_RESET_RLC (1 << 2) /* RLC */ 10786f2043ceSAlex Deucher #define SOFT_RESET_GFX (1 << 16) /* GFX */ 10796f2043ceSAlex Deucher #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 10806f2043ceSAlex Deucher #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 10816f2043ceSAlex Deucher #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 10826f2043ceSAlex Deucher 1083a59781bbSAlex Deucher #define GRBM_INT_CNTL 0x8060 1084a59781bbSAlex Deucher # define RDERR_INT_ENABLE (1 << 0) 1085a59781bbSAlex Deucher # define GUI_IDLE_INT_ENABLE (1 << 19) 1086a59781bbSAlex Deucher 1087963e81f9SAlex Deucher #define CP_CPC_STATUS 0x8210 1088963e81f9SAlex Deucher #define CP_CPC_BUSY_STAT 0x8214 1089963e81f9SAlex Deucher #define CP_CPC_STALLED_STAT1 0x8218 1090963e81f9SAlex Deucher #define CP_CPF_STATUS 0x821c 1091963e81f9SAlex Deucher #define CP_CPF_BUSY_STAT 0x8220 1092963e81f9SAlex Deucher #define CP_CPF_STALLED_STAT1 0x8224 1093963e81f9SAlex Deucher 10946f2043ceSAlex Deucher #define CP_MEC_CNTL 0x8234 10956f2043ceSAlex Deucher #define MEC_ME2_HALT (1 << 28) 10966f2043ceSAlex Deucher #define MEC_ME1_HALT (1 << 30) 10976f2043ceSAlex Deucher 1098841cf442SAlex Deucher #define CP_MEC_CNTL 0x8234 1099841cf442SAlex Deucher #define MEC_ME2_HALT (1 << 28) 1100841cf442SAlex Deucher #define MEC_ME1_HALT (1 << 30) 1101841cf442SAlex Deucher 1102963e81f9SAlex Deucher #define CP_STALLED_STAT3 0x8670 1103963e81f9SAlex Deucher #define CP_STALLED_STAT1 0x8674 1104963e81f9SAlex Deucher #define CP_STALLED_STAT2 0x8678 1105963e81f9SAlex Deucher 1106963e81f9SAlex Deucher #define CP_STAT 0x8680 1107963e81f9SAlex Deucher 11086f2043ceSAlex Deucher #define CP_ME_CNTL 0x86D8 11096f2043ceSAlex Deucher #define CP_CE_HALT (1 << 24) 11106f2043ceSAlex Deucher #define CP_PFP_HALT (1 << 26) 11116f2043ceSAlex Deucher #define CP_ME_HALT (1 << 28) 11126f2043ceSAlex Deucher 1113841cf442SAlex Deucher #define CP_RB0_RPTR 0x8700 1114841cf442SAlex Deucher #define CP_RB_WPTR_DELAY 0x8704 111522c775ceSAlex Deucher #define CP_RB_WPTR_POLL_CNTL 0x8708 111622c775ceSAlex Deucher #define IDLE_POLL_COUNT(x) ((x) << 16) 111722c775ceSAlex Deucher #define IDLE_POLL_COUNT_MASK (0xffff << 16) 1118841cf442SAlex Deucher 11198cc1a532SAlex Deucher #define CP_MEQ_THRESHOLDS 0x8764 11208cc1a532SAlex Deucher #define MEQ1_START(x) ((x) << 0) 11218cc1a532SAlex Deucher #define MEQ2_START(x) ((x) << 8) 11228cc1a532SAlex Deucher 11238cc1a532SAlex Deucher #define VGT_VTX_VECT_EJECT_REG 0x88B0 11248cc1a532SAlex Deucher 11258cc1a532SAlex Deucher #define VGT_CACHE_INVALIDATION 0x88C4 11268cc1a532SAlex Deucher #define CACHE_INVALIDATION(x) ((x) << 0) 11278cc1a532SAlex Deucher #define VC_ONLY 0 11288cc1a532SAlex Deucher #define TC_ONLY 1 11298cc1a532SAlex Deucher #define VC_AND_TC 2 11308cc1a532SAlex Deucher #define AUTO_INVLD_EN(x) ((x) << 6) 11318cc1a532SAlex Deucher #define NO_AUTO 0 11328cc1a532SAlex Deucher #define ES_AUTO 1 11338cc1a532SAlex Deucher #define GS_AUTO 2 11348cc1a532SAlex Deucher #define ES_AND_GS_AUTO 3 11358cc1a532SAlex Deucher 11368cc1a532SAlex Deucher #define VGT_GS_VERTEX_REUSE 0x88D4 11378cc1a532SAlex Deucher 11388cc1a532SAlex Deucher #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 11398cc1a532SAlex Deucher #define INACTIVE_CUS_MASK 0xFFFF0000 11408cc1a532SAlex Deucher #define INACTIVE_CUS_SHIFT 16 11418cc1a532SAlex Deucher #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 11428cc1a532SAlex Deucher 11438cc1a532SAlex Deucher #define PA_CL_ENHANCE 0x8A14 11448cc1a532SAlex Deucher #define CLIP_VTX_REORDER_ENA (1 << 0) 11458cc1a532SAlex Deucher #define NUM_CLIP_SEQ(x) ((x) << 1) 11468cc1a532SAlex Deucher 11478cc1a532SAlex Deucher #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 11488cc1a532SAlex Deucher #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 11498cc1a532SAlex Deucher #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 11508cc1a532SAlex Deucher 11518cc1a532SAlex Deucher #define PA_SC_FIFO_SIZE 0x8BCC 11528cc1a532SAlex Deucher #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 11538cc1a532SAlex Deucher #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 11548cc1a532SAlex Deucher #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 11558cc1a532SAlex Deucher #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 11568cc1a532SAlex Deucher 11578cc1a532SAlex Deucher #define PA_SC_ENHANCE 0x8BF0 11588cc1a532SAlex Deucher #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 11598cc1a532SAlex Deucher #define DISABLE_PA_SC_GUIDANCE (1 << 13) 11608cc1a532SAlex Deucher 11618cc1a532SAlex Deucher #define SQ_CONFIG 0x8C00 11628cc1a532SAlex Deucher 11631c49165dSAlex Deucher #define SH_MEM_BASES 0x8C28 11641c49165dSAlex Deucher /* if PTR32, these are the bases for scratch and lds */ 11651c49165dSAlex Deucher #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 11661c49165dSAlex Deucher #define SHARED_BASE(x) ((x) << 16) /* LDS */ 11671c49165dSAlex Deucher #define SH_MEM_APE1_BASE 0x8C2C 11681c49165dSAlex Deucher /* if PTR32, this is the base location of GPUVM */ 11691c49165dSAlex Deucher #define SH_MEM_APE1_LIMIT 0x8C30 11701c49165dSAlex Deucher /* if PTR32, this is the upper limit of GPUVM */ 11711c49165dSAlex Deucher #define SH_MEM_CONFIG 0x8C34 11721c49165dSAlex Deucher #define PTR32 (1 << 0) 11731c49165dSAlex Deucher #define ALIGNMENT_MODE(x) ((x) << 2) 11741c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD 0 11751c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 11761c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_STRICT 2 11771c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 11781c49165dSAlex Deucher #define DEFAULT_MTYPE(x) ((x) << 4) 11791c49165dSAlex Deucher #define APE1_MTYPE(x) ((x) << 7) 1180e28740ecSOded Gabbay /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 1181e28740ecSOded Gabbay #define MTYPE_CACHED 0 1182e28740ecSOded Gabbay #define MTYPE_NONCACHED 3 11831c49165dSAlex Deucher 11848cc1a532SAlex Deucher #define SX_DEBUG_1 0x9060 11858cc1a532SAlex Deucher 11868cc1a532SAlex Deucher #define SPI_CONFIG_CNTL 0x9100 11878cc1a532SAlex Deucher 11888cc1a532SAlex Deucher #define SPI_CONFIG_CNTL_1 0x913C 11898cc1a532SAlex Deucher #define VTX_DONE_DELAY(x) ((x) << 0) 11908cc1a532SAlex Deucher #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 11918cc1a532SAlex Deucher 11928cc1a532SAlex Deucher #define TA_CNTL_AUX 0x9508 11938cc1a532SAlex Deucher 11948cc1a532SAlex Deucher #define DB_DEBUG 0x9830 11958cc1a532SAlex Deucher #define DB_DEBUG2 0x9834 11968cc1a532SAlex Deucher #define DB_DEBUG3 0x9838 11978cc1a532SAlex Deucher 11988cc1a532SAlex Deucher #define CC_RB_BACKEND_DISABLE 0x98F4 11998cc1a532SAlex Deucher #define BACKEND_DISABLE(x) ((x) << 16) 12008cc1a532SAlex Deucher #define GB_ADDR_CONFIG 0x98F8 12018cc1a532SAlex Deucher #define NUM_PIPES(x) ((x) << 0) 12028cc1a532SAlex Deucher #define NUM_PIPES_MASK 0x00000007 12038cc1a532SAlex Deucher #define NUM_PIPES_SHIFT 0 12048cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 12058cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 12068cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_SHIFT 4 12078cc1a532SAlex Deucher #define NUM_SHADER_ENGINES(x) ((x) << 12) 12088cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_MASK 0x00003000 12098cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_SHIFT 12 12108cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 12118cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 12128cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 12138cc1a532SAlex Deucher #define ROW_SIZE(x) ((x) << 28) 12148cc1a532SAlex Deucher #define ROW_SIZE_MASK 0x30000000 12158cc1a532SAlex Deucher #define ROW_SIZE_SHIFT 28 12168cc1a532SAlex Deucher 12178cc1a532SAlex Deucher #define GB_TILE_MODE0 0x9910 12188cc1a532SAlex Deucher # define ARRAY_MODE(x) ((x) << 2) 12198cc1a532SAlex Deucher # define ARRAY_LINEAR_GENERAL 0 12208cc1a532SAlex Deucher # define ARRAY_LINEAR_ALIGNED 1 12218cc1a532SAlex Deucher # define ARRAY_1D_TILED_THIN1 2 12228cc1a532SAlex Deucher # define ARRAY_2D_TILED_THIN1 4 12238cc1a532SAlex Deucher # define ARRAY_PRT_TILED_THIN1 5 12248cc1a532SAlex Deucher # define ARRAY_PRT_2D_TILED_THIN1 6 12258cc1a532SAlex Deucher # define PIPE_CONFIG(x) ((x) << 6) 12268cc1a532SAlex Deucher # define ADDR_SURF_P2 0 12278cc1a532SAlex Deucher # define ADDR_SURF_P4_8x16 4 12288cc1a532SAlex Deucher # define ADDR_SURF_P4_16x16 5 12298cc1a532SAlex Deucher # define ADDR_SURF_P4_16x32 6 12308cc1a532SAlex Deucher # define ADDR_SURF_P4_32x32 7 12318cc1a532SAlex Deucher # define ADDR_SURF_P8_16x16_8x16 8 12328cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_8x16 9 12338cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_8x16 10 12348cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_16x16 11 12358cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x16 12 12368cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x32 13 12378cc1a532SAlex Deucher # define ADDR_SURF_P8_32x64_32x32 14 123821e438afSAlex Deucher # define ADDR_SURF_P16_32x32_8x16 16 123921e438afSAlex Deucher # define ADDR_SURF_P16_32x32_16x16 17 12408cc1a532SAlex Deucher # define TILE_SPLIT(x) ((x) << 11) 12418cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_64B 0 12428cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_128B 1 12438cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_256B 2 12448cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_512B 3 12458cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_1KB 4 12468cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_2KB 5 12478cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_4KB 6 12488cc1a532SAlex Deucher # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 12498cc1a532SAlex Deucher # define ADDR_SURF_DISPLAY_MICRO_TILING 0 12508cc1a532SAlex Deucher # define ADDR_SURF_THIN_MICRO_TILING 1 12518cc1a532SAlex Deucher # define ADDR_SURF_DEPTH_MICRO_TILING 2 12528cc1a532SAlex Deucher # define ADDR_SURF_ROTATED_MICRO_TILING 3 12538cc1a532SAlex Deucher # define SAMPLE_SPLIT(x) ((x) << 25) 12548cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_1 0 12558cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_2 1 12568cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_4 2 12578cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_8 3 12588cc1a532SAlex Deucher 12598cc1a532SAlex Deucher #define GB_MACROTILE_MODE0 0x9990 12608cc1a532SAlex Deucher # define BANK_WIDTH(x) ((x) << 0) 12618cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_1 0 12628cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_2 1 12638cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_4 2 12648cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_8 3 12658cc1a532SAlex Deucher # define BANK_HEIGHT(x) ((x) << 2) 12668cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_1 0 12678cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_2 1 12688cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_4 2 12698cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_8 3 12708cc1a532SAlex Deucher # define MACRO_TILE_ASPECT(x) ((x) << 4) 12718cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_1 0 12728cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_2 1 12738cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_4 2 12748cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_8 3 12758cc1a532SAlex Deucher # define NUM_BANKS(x) ((x) << 6) 12768cc1a532SAlex Deucher # define ADDR_SURF_2_BANK 0 12778cc1a532SAlex Deucher # define ADDR_SURF_4_BANK 1 12788cc1a532SAlex Deucher # define ADDR_SURF_8_BANK 2 12798cc1a532SAlex Deucher # define ADDR_SURF_16_BANK 3 12808cc1a532SAlex Deucher 12818cc1a532SAlex Deucher #define CB_HW_CONTROL 0x9A10 12828cc1a532SAlex Deucher 12838cc1a532SAlex Deucher #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 12848cc1a532SAlex Deucher #define BACKEND_DISABLE_MASK 0x00FF0000 12858cc1a532SAlex Deucher #define BACKEND_DISABLE_SHIFT 16 12868cc1a532SAlex Deucher 12878cc1a532SAlex Deucher #define TCP_CHAN_STEER_LO 0xac0c 12888cc1a532SAlex Deucher #define TCP_CHAN_STEER_HI 0xac10 12898cc1a532SAlex Deucher 12901c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY0 0xAC68 12911c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 12921c49165dSAlex Deucher #define TC_CFG_L1_STORE_POLICY 0xAC70 12931c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY0 0xAC74 12941c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY1 0xAC78 12951c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY0 0xAC7C 12961c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY1 0xAC80 12971c49165dSAlex Deucher #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 12981c49165dSAlex Deucher #define TC_CFG_L1_VOLATILE 0xAC88 12991c49165dSAlex Deucher #define TC_CFG_L2_VOLATILE 0xAC8C 13001c49165dSAlex Deucher 1301841cf442SAlex Deucher #define CP_RB0_BASE 0xC100 1302841cf442SAlex Deucher #define CP_RB0_CNTL 0xC104 1303841cf442SAlex Deucher #define RB_BUFSZ(x) ((x) << 0) 1304841cf442SAlex Deucher #define RB_BLKSZ(x) ((x) << 8) 1305841cf442SAlex Deucher #define BUF_SWAP_32BIT (2 << 16) 1306841cf442SAlex Deucher #define RB_NO_UPDATE (1 << 27) 1307841cf442SAlex Deucher #define RB_RPTR_WR_ENA (1 << 31) 1308841cf442SAlex Deucher 1309841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR 0xC10C 1310841cf442SAlex Deucher #define RB_RPTR_SWAP_32BIT (2 << 0) 1311841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR_HI 0xC110 1312841cf442SAlex Deucher #define CP_RB0_WPTR 0xC114 1313841cf442SAlex Deucher 1314841cf442SAlex Deucher #define CP_DEVICE_ID 0xC12C 1315841cf442SAlex Deucher #define CP_ENDIAN_SWAP 0xC140 1316841cf442SAlex Deucher #define CP_RB_VMID 0xC144 1317841cf442SAlex Deucher 1318841cf442SAlex Deucher #define CP_PFP_UCODE_ADDR 0xC150 1319841cf442SAlex Deucher #define CP_PFP_UCODE_DATA 0xC154 1320841cf442SAlex Deucher #define CP_ME_RAM_RADDR 0xC158 1321841cf442SAlex Deucher #define CP_ME_RAM_WADDR 0xC15C 1322841cf442SAlex Deucher #define CP_ME_RAM_DATA 0xC160 1323841cf442SAlex Deucher 1324841cf442SAlex Deucher #define CP_CE_UCODE_ADDR 0xC168 1325841cf442SAlex Deucher #define CP_CE_UCODE_DATA 0xC16C 1326841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_ADDR 0xC170 1327841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_DATA 0xC174 1328841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_ADDR 0xC178 1329841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_DATA 0xC17C 1330841cf442SAlex Deucher 1331f6796caeSAlex Deucher #define CP_INT_CNTL_RING0 0xC1A8 1332f6796caeSAlex Deucher # define CNTX_BUSY_INT_ENABLE (1 << 19) 1333f6796caeSAlex Deucher # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1334f6796caeSAlex Deucher # define PRIV_INSTR_INT_ENABLE (1 << 22) 1335f6796caeSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 1336d36b94fcSOded Gabbay # define OPCODE_ERROR_INT_ENABLE (1 << 24) 1337f6796caeSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 1338f6796caeSAlex Deucher # define CP_RINGID2_INT_ENABLE (1 << 29) 1339f6796caeSAlex Deucher # define CP_RINGID1_INT_ENABLE (1 << 30) 1340f6796caeSAlex Deucher # define CP_RINGID0_INT_ENABLE (1 << 31) 1341f6796caeSAlex Deucher 1342a59781bbSAlex Deucher #define CP_INT_STATUS_RING0 0xC1B4 1343a59781bbSAlex Deucher # define PRIV_INSTR_INT_STAT (1 << 22) 1344a59781bbSAlex Deucher # define PRIV_REG_INT_STAT (1 << 23) 1345a59781bbSAlex Deucher # define TIME_STAMP_INT_STAT (1 << 26) 1346a59781bbSAlex Deucher # define CP_RINGID2_INT_STAT (1 << 29) 1347a59781bbSAlex Deucher # define CP_RINGID1_INT_STAT (1 << 30) 1348a59781bbSAlex Deucher # define CP_RINGID0_INT_STAT (1 << 31) 1349a59781bbSAlex Deucher 135022c775ceSAlex Deucher #define CP_MEM_SLP_CNTL 0xC1E4 135122c775ceSAlex Deucher # define CP_MEM_LS_EN (1 << 0) 135222c775ceSAlex Deucher 1353963e81f9SAlex Deucher #define CP_CPF_DEBUG 0xC200 1354963e81f9SAlex Deucher 1355963e81f9SAlex Deucher #define CP_PQ_WPTR_POLL_CNTL 0xC20C 1356963e81f9SAlex Deucher #define WPTR_POLL_EN (1 << 31) 1357963e81f9SAlex Deucher 1358a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_CNTL 0xC214 1359a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_CNTL 0xC218 1360a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_CNTL 0xC21C 1361a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_CNTL 0xC220 1362a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_CNTL 0xC224 1363a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_CNTL 0xC228 1364a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_CNTL 0xC22C 1365a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_CNTL 0xC230 1366a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 1367a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 1368a59781bbSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 1369a59781bbSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 1370a59781bbSAlex Deucher # define GENERIC2_INT_ENABLE (1 << 29) 1371a59781bbSAlex Deucher # define GENERIC1_INT_ENABLE (1 << 30) 1372a59781bbSAlex Deucher # define GENERIC0_INT_ENABLE (1 << 31) 1373a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_STATUS 0xC214 1374a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_STATUS 0xC218 1375a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_STATUS 0xC21C 1376a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_STATUS 0xC220 1377a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_STATUS 0xC224 1378a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_STATUS 0xC228 1379a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_STATUS 0xC22C 1380a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_STATUS 0xC230 1381a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 1382a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 1383a59781bbSAlex Deucher # define PRIV_REG_INT_STATUS (1 << 23) 1384a59781bbSAlex Deucher # define TIME_STAMP_INT_STATUS (1 << 26) 1385a59781bbSAlex Deucher # define GENERIC2_INT_STATUS (1 << 29) 1386a59781bbSAlex Deucher # define GENERIC1_INT_STATUS (1 << 30) 1387a59781bbSAlex Deucher # define GENERIC0_INT_STATUS (1 << 31) 1388a59781bbSAlex Deucher 1389841cf442SAlex Deucher #define CP_MAX_CONTEXT 0xC2B8 1390841cf442SAlex Deucher 1391841cf442SAlex Deucher #define CP_RB0_BASE_HI 0xC2C4 1392841cf442SAlex Deucher 1393f6796caeSAlex Deucher #define RLC_CNTL 0xC300 1394f6796caeSAlex Deucher # define RLC_ENABLE (1 << 0) 1395f6796caeSAlex Deucher 1396f6796caeSAlex Deucher #define RLC_MC_CNTL 0xC30C 1397f6796caeSAlex Deucher 139822c775ceSAlex Deucher #define RLC_MEM_SLP_CNTL 0xC318 139922c775ceSAlex Deucher # define RLC_MEM_LS_EN (1 << 0) 140022c775ceSAlex Deucher 1401f6796caeSAlex Deucher #define RLC_LB_CNTR_MAX 0xC348 1402f6796caeSAlex Deucher 1403f6796caeSAlex Deucher #define RLC_LB_CNTL 0xC364 1404866d83deSAlex Deucher # define LOAD_BALANCE_ENABLE (1 << 0) 1405f6796caeSAlex Deucher 1406f6796caeSAlex Deucher #define RLC_LB_CNTR_INIT 0xC36C 1407f6796caeSAlex Deucher 1408f6796caeSAlex Deucher #define RLC_SAVE_AND_RESTORE_BASE 0xC374 140922c775ceSAlex Deucher #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 141022c775ceSAlex Deucher #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 141122c775ceSAlex Deucher #define RLC_PG_DELAY_2 0xC37C 1412f6796caeSAlex Deucher 1413f6796caeSAlex Deucher #define RLC_GPM_UCODE_ADDR 0xC388 1414f6796caeSAlex Deucher #define RLC_GPM_UCODE_DATA 0xC38C 141544fa346fSAlex Deucher #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 141644fa346fSAlex Deucher #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 141744fa346fSAlex Deucher #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 1418f6796caeSAlex Deucher #define RLC_UCODE_CNTL 0xC39C 1419f6796caeSAlex Deucher 142022c775ceSAlex Deucher #define RLC_GPM_STAT 0xC400 142122c775ceSAlex Deucher # define RLC_GPM_BUSY (1 << 0) 1422a412fce0SAlex Deucher # define GFX_POWER_STATUS (1 << 1) 1423a412fce0SAlex Deucher # define GFX_CLOCK_STATUS (1 << 2) 142422c775ceSAlex Deucher 142522c775ceSAlex Deucher #define RLC_PG_CNTL 0xC40C 142622c775ceSAlex Deucher # define GFX_PG_ENABLE (1 << 0) 142722c775ceSAlex Deucher # define GFX_PG_SRC (1 << 1) 142822c775ceSAlex Deucher # define DYN_PER_CU_PG_ENABLE (1 << 2) 142922c775ceSAlex Deucher # define STATIC_PER_CU_PG_ENABLE (1 << 3) 143022c775ceSAlex Deucher # define DISABLE_GDS_PG (1 << 13) 143122c775ceSAlex Deucher # define DISABLE_CP_PG (1 << 15) 143222c775ceSAlex Deucher # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 143322c775ceSAlex Deucher # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 143422c775ceSAlex Deucher 143522c775ceSAlex Deucher #define RLC_CGTT_MGCG_OVERRIDE 0xC420 1436f6796caeSAlex Deucher #define RLC_CGCG_CGLS_CTRL 0xC424 143722c775ceSAlex Deucher # define CGCG_EN (1 << 0) 143822c775ceSAlex Deucher # define CGLS_EN (1 << 1) 143922c775ceSAlex Deucher 144022c775ceSAlex Deucher #define RLC_PG_DELAY 0xC434 1441f6796caeSAlex Deucher 1442f6796caeSAlex Deucher #define RLC_LB_INIT_CU_MASK 0xC43C 1443f6796caeSAlex Deucher 1444f6796caeSAlex Deucher #define RLC_LB_PARAMS 0xC444 1445f6796caeSAlex Deucher 144622c775ceSAlex Deucher #define RLC_PG_AO_CU_MASK 0xC44C 144722c775ceSAlex Deucher 144822c775ceSAlex Deucher #define RLC_MAX_PG_CU 0xC450 144922c775ceSAlex Deucher # define MAX_PU_CU(x) ((x) << 0) 145022c775ceSAlex Deucher # define MAX_PU_CU_MASK (0xff << 0) 145122c775ceSAlex Deucher #define RLC_AUTO_PG_CTRL 0xC454 145222c775ceSAlex Deucher # define AUTO_PG_EN (1 << 0) 145322c775ceSAlex Deucher # define GRBM_REG_SGIT(x) ((x) << 3) 145422c775ceSAlex Deucher # define GRBM_REG_SGIT_MASK (0xffff << 3) 145522c775ceSAlex Deucher 145622c775ceSAlex Deucher #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 145722c775ceSAlex Deucher #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 145822c775ceSAlex Deucher #define RLC_SERDES_WR_CTRL 0xC47C 145922c775ceSAlex Deucher #define BPM_ADDR(x) ((x) << 0) 146022c775ceSAlex Deucher #define BPM_ADDR_MASK (0xff << 0) 146122c775ceSAlex Deucher #define CGLS_ENABLE (1 << 16) 146222c775ceSAlex Deucher #define CGCG_OVERRIDE_0 (1 << 20) 146322c775ceSAlex Deucher #define MGCG_OVERRIDE_0 (1 << 22) 146422c775ceSAlex Deucher #define MGCG_OVERRIDE_1 (1 << 23) 146522c775ceSAlex Deucher 1466f6796caeSAlex Deucher #define RLC_SERDES_CU_MASTER_BUSY 0xC484 1467f6796caeSAlex Deucher #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 1468f6796caeSAlex Deucher # define SE_MASTER_BUSY_MASK 0x0000ffff 1469f6796caeSAlex Deucher # define GC_MASTER_BUSY (1 << 16) 1470f6796caeSAlex Deucher # define TC0_MASTER_BUSY (1 << 17) 1471f6796caeSAlex Deucher # define TC1_MASTER_BUSY (1 << 18) 1472f6796caeSAlex Deucher 1473f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_ADDR 0xC4B0 1474f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_DATA 0xC4B4 1475f6796caeSAlex Deucher 1476a412fce0SAlex Deucher #define RLC_GPR_REG2 0xC4E8 1477a412fce0SAlex Deucher #define REQ 0x00000001 1478a412fce0SAlex Deucher #define MESSAGE(x) ((x) << 1) 1479a412fce0SAlex Deucher #define MESSAGE_MASK 0x0000001e 1480a412fce0SAlex Deucher #define MSG_ENTER_RLC_SAFE_MODE 1 1481a412fce0SAlex Deucher #define MSG_EXIT_RLC_SAFE_MODE 0 1482a412fce0SAlex Deucher 1483963e81f9SAlex Deucher #define CP_HPD_EOP_BASE_ADDR 0xC904 1484963e81f9SAlex Deucher #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1485963e81f9SAlex Deucher #define CP_HPD_EOP_VMID 0xC90C 1486963e81f9SAlex Deucher #define CP_HPD_EOP_CONTROL 0xC910 1487963e81f9SAlex Deucher #define EOP_SIZE(x) ((x) << 0) 1488963e81f9SAlex Deucher #define EOP_SIZE_MASK (0x3f << 0) 1489963e81f9SAlex Deucher #define CP_MQD_BASE_ADDR 0xC914 1490963e81f9SAlex Deucher #define CP_MQD_BASE_ADDR_HI 0xC918 1491963e81f9SAlex Deucher #define CP_HQD_ACTIVE 0xC91C 1492963e81f9SAlex Deucher #define CP_HQD_VMID 0xC920 1493963e81f9SAlex Deucher 1494e28740ecSOded Gabbay #define CP_HQD_PERSISTENT_STATE 0xC924u 1495e28740ecSOded Gabbay #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) 1496e28740ecSOded Gabbay 1497e28740ecSOded Gabbay #define CP_HQD_PIPE_PRIORITY 0xC928u 1498e28740ecSOded Gabbay #define CP_HQD_QUEUE_PRIORITY 0xC92Cu 1499e28740ecSOded Gabbay #define CP_HQD_QUANTUM 0xC930u 1500e28740ecSOded Gabbay #define QUANTUM_EN 1U 1501e28740ecSOded Gabbay #define QUANTUM_SCALE_1MS (1U << 4) 1502e28740ecSOded Gabbay #define QUANTUM_DURATION(x) ((x) << 8) 1503e28740ecSOded Gabbay 1504963e81f9SAlex Deucher #define CP_HQD_PQ_BASE 0xC934 1505963e81f9SAlex Deucher #define CP_HQD_PQ_BASE_HI 0xC938 1506963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR 0xC93C 1507963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 1508963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 1509963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 1510963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 1511963e81f9SAlex Deucher #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 1512963e81f9SAlex Deucher #define DOORBELL_OFFSET(x) ((x) << 2) 1513963e81f9SAlex Deucher #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 1514963e81f9SAlex Deucher #define DOORBELL_SOURCE (1 << 28) 1515963e81f9SAlex Deucher #define DOORBELL_SCHD_HIT (1 << 29) 1516963e81f9SAlex Deucher #define DOORBELL_EN (1 << 30) 1517963e81f9SAlex Deucher #define DOORBELL_HIT (1 << 31) 1518963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR 0xC954 1519963e81f9SAlex Deucher #define CP_HQD_PQ_CONTROL 0xC958 1520963e81f9SAlex Deucher #define QUEUE_SIZE(x) ((x) << 0) 1521963e81f9SAlex Deucher #define QUEUE_SIZE_MASK (0x3f << 0) 1522963e81f9SAlex Deucher #define RPTR_BLOCK_SIZE(x) ((x) << 8) 1523963e81f9SAlex Deucher #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 1524963e81f9SAlex Deucher #define PQ_VOLATILE (1 << 26) 1525963e81f9SAlex Deucher #define NO_UPDATE_RPTR (1 << 27) 1526963e81f9SAlex Deucher #define UNORD_DISPATCH (1 << 28) 1527963e81f9SAlex Deucher #define ROQ_PQ_IB_FLIP (1 << 29) 1528963e81f9SAlex Deucher #define PRIV_STATE (1 << 30) 1529963e81f9SAlex Deucher #define KMD_QUEUE (1 << 31) 1530963e81f9SAlex Deucher 1531e28740ecSOded Gabbay #define CP_HQD_IB_BASE_ADDR 0xC95Cu 1532e28740ecSOded Gabbay #define CP_HQD_IB_BASE_ADDR_HI 0xC960u 1533e28740ecSOded Gabbay #define CP_HQD_IB_RPTR 0xC964u 1534e28740ecSOded Gabbay #define CP_HQD_IB_CONTROL 0xC968u 1535e28740ecSOded Gabbay #define IB_ATC_EN (1U << 23) 1536e28740ecSOded Gabbay #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) 1537e28740ecSOded Gabbay 1538963e81f9SAlex Deucher #define CP_HQD_DEQUEUE_REQUEST 0xC974 1539e28740ecSOded Gabbay #define DEQUEUE_REQUEST_DRAIN 1 1540e28740ecSOded Gabbay #define DEQUEUE_REQUEST_RESET 2 1541963e81f9SAlex Deucher 1542963e81f9SAlex Deucher #define CP_MQD_CONTROL 0xC99C 1543963e81f9SAlex Deucher #define MQD_VMID(x) ((x) << 0) 1544963e81f9SAlex Deucher #define MQD_VMID_MASK (0xf << 0) 1545963e81f9SAlex Deucher 1546e28740ecSOded Gabbay #define CP_HQD_SEMA_CMD 0xC97Cu 1547e28740ecSOded Gabbay #define CP_HQD_MSG_TYPE 0xC980u 1548e28740ecSOded Gabbay #define CP_HQD_ATOMIC0_PREOP_LO 0xC984u 1549e28740ecSOded Gabbay #define CP_HQD_ATOMIC0_PREOP_HI 0xC988u 1550e28740ecSOded Gabbay #define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu 1551e28740ecSOded Gabbay #define CP_HQD_ATOMIC1_PREOP_HI 0xC990u 1552e28740ecSOded Gabbay #define CP_HQD_HQ_SCHEDULER0 0xC994u 1553e28740ecSOded Gabbay #define CP_HQD_HQ_SCHEDULER1 0xC998u 1554e28740ecSOded Gabbay 1555e28740ecSOded Gabbay #define SH_STATIC_MEM_CONFIG 0x9604u 1556e28740ecSOded Gabbay 155722c775ceSAlex Deucher #define DB_RENDER_CONTROL 0x28000 155822c775ceSAlex Deucher 15598cc1a532SAlex Deucher #define PA_SC_RASTER_CONFIG 0x28350 15608cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_0 0 15618cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_1 1 15628cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_2 2 15638cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_3 3 1564fc821b70SAlex Deucher #define PKR_MAP(x) ((x) << 8) 15658cc1a532SAlex Deucher 15662cae3bc3SAlex Deucher #define VGT_EVENT_INITIATOR 0x28a90 15672cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 15682cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 15692cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 15702cae3bc3SAlex Deucher # define CACHE_FLUSH_TS (4 << 0) 15712cae3bc3SAlex Deucher # define CACHE_FLUSH (6 << 0) 15722cae3bc3SAlex Deucher # define CS_PARTIAL_FLUSH (7 << 0) 15732cae3bc3SAlex Deucher # define VGT_STREAMOUT_RESET (10 << 0) 15742cae3bc3SAlex Deucher # define END_OF_PIPE_INCR_DE (11 << 0) 15752cae3bc3SAlex Deucher # define END_OF_PIPE_IB_END (12 << 0) 15762cae3bc3SAlex Deucher # define RST_PIX_CNT (13 << 0) 15772cae3bc3SAlex Deucher # define VS_PARTIAL_FLUSH (15 << 0) 15782cae3bc3SAlex Deucher # define PS_PARTIAL_FLUSH (16 << 0) 15792cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 15802cae3bc3SAlex Deucher # define ZPASS_DONE (21 << 0) 15812cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 15822cae3bc3SAlex Deucher # define PERFCOUNTER_START (23 << 0) 15832cae3bc3SAlex Deucher # define PERFCOUNTER_STOP (24 << 0) 15842cae3bc3SAlex Deucher # define PIPELINESTAT_START (25 << 0) 15852cae3bc3SAlex Deucher # define PIPELINESTAT_STOP (26 << 0) 15862cae3bc3SAlex Deucher # define PERFCOUNTER_SAMPLE (27 << 0) 15872cae3bc3SAlex Deucher # define SAMPLE_PIPELINESTAT (30 << 0) 15882cae3bc3SAlex Deucher # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 15892cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS (32 << 0) 15902cae3bc3SAlex Deucher # define RESET_VTX_CNT (33 << 0) 15912cae3bc3SAlex Deucher # define VGT_FLUSH (36 << 0) 15922cae3bc3SAlex Deucher # define BOTTOM_OF_PIPE_TS (40 << 0) 15932cae3bc3SAlex Deucher # define DB_CACHE_FLUSH_AND_INV (42 << 0) 15942cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 15952cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_META (44 << 0) 15962cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 15972cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_META (46 << 0) 15982cae3bc3SAlex Deucher # define CS_DONE (47 << 0) 15992cae3bc3SAlex Deucher # define PS_DONE (48 << 0) 16002cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 16012cae3bc3SAlex Deucher # define THREAD_TRACE_START (51 << 0) 16022cae3bc3SAlex Deucher # define THREAD_TRACE_STOP (52 << 0) 16032cae3bc3SAlex Deucher # define THREAD_TRACE_FLUSH (54 << 0) 16042cae3bc3SAlex Deucher # define THREAD_TRACE_FINISH (55 << 0) 16052cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 16062cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_DUMP (57 << 0) 16072cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_RESET (58 << 0) 16082cae3bc3SAlex Deucher 1609841cf442SAlex Deucher #define SCRATCH_REG0 0x30100 1610841cf442SAlex Deucher #define SCRATCH_REG1 0x30104 1611841cf442SAlex Deucher #define SCRATCH_REG2 0x30108 1612841cf442SAlex Deucher #define SCRATCH_REG3 0x3010C 1613841cf442SAlex Deucher #define SCRATCH_REG4 0x30110 1614841cf442SAlex Deucher #define SCRATCH_REG5 0x30114 1615841cf442SAlex Deucher #define SCRATCH_REG6 0x30118 1616841cf442SAlex Deucher #define SCRATCH_REG7 0x3011C 1617841cf442SAlex Deucher 1618841cf442SAlex Deucher #define SCRATCH_UMSK 0x30140 1619841cf442SAlex Deucher #define SCRATCH_ADDR 0x30144 1620841cf442SAlex Deucher 1621841cf442SAlex Deucher #define CP_SEM_WAIT_TIMER 0x301BC 1622841cf442SAlex Deucher 1623841cf442SAlex Deucher #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 1624841cf442SAlex Deucher 16252cae3bc3SAlex Deucher #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 16262cae3bc3SAlex Deucher 16278cc1a532SAlex Deucher #define GRBM_GFX_INDEX 0x30800 16288cc1a532SAlex Deucher #define INSTANCE_INDEX(x) ((x) << 0) 16298cc1a532SAlex Deucher #define SH_INDEX(x) ((x) << 8) 16308cc1a532SAlex Deucher #define SE_INDEX(x) ((x) << 16) 16318cc1a532SAlex Deucher #define SH_BROADCAST_WRITES (1 << 29) 16328cc1a532SAlex Deucher #define INSTANCE_BROADCAST_WRITES (1 << 30) 16338cc1a532SAlex Deucher #define SE_BROADCAST_WRITES (1 << 31) 16348cc1a532SAlex Deucher 16358cc1a532SAlex Deucher #define VGT_ESGS_RING_SIZE 0x30900 16368cc1a532SAlex Deucher #define VGT_GSVS_RING_SIZE 0x30904 16378cc1a532SAlex Deucher #define VGT_PRIMITIVE_TYPE 0x30908 16388cc1a532SAlex Deucher #define VGT_INDEX_TYPE 0x3090C 16398cc1a532SAlex Deucher 16408cc1a532SAlex Deucher #define VGT_NUM_INDICES 0x30930 16418cc1a532SAlex Deucher #define VGT_NUM_INSTANCES 0x30934 16428cc1a532SAlex Deucher #define VGT_TF_RING_SIZE 0x30938 16438cc1a532SAlex Deucher #define VGT_HS_OFFCHIP_PARAM 0x3093C 16448cc1a532SAlex Deucher #define VGT_TF_MEMORY_BASE 0x30940 16458cc1a532SAlex Deucher 16468cc1a532SAlex Deucher #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 16478cc1a532SAlex Deucher #define PA_SC_LINE_STIPPLE_STATE 0x30a04 16488cc1a532SAlex Deucher 16498cc1a532SAlex Deucher #define SQC_CACHES 0x30d20 16508cc1a532SAlex Deucher 16518cc1a532SAlex Deucher #define CP_PERFMON_CNTL 0x36020 16528cc1a532SAlex Deucher 165322c775ceSAlex Deucher #define CGTS_SM_CTRL_REG 0x3c000 165422c775ceSAlex Deucher #define SM_MODE(x) ((x) << 17) 165522c775ceSAlex Deucher #define SM_MODE_MASK (0x7 << 17) 165622c775ceSAlex Deucher #define SM_MODE_ENABLE (1 << 20) 165722c775ceSAlex Deucher #define CGTS_OVERRIDE (1 << 21) 165822c775ceSAlex Deucher #define CGTS_LS_OVERRIDE (1 << 22) 165922c775ceSAlex Deucher #define ON_MONITOR_ADD_EN (1 << 23) 166022c775ceSAlex Deucher #define ON_MONITOR_ADD(x) ((x) << 24) 166122c775ceSAlex Deucher #define ON_MONITOR_ADD_MASK (0xff << 24) 166222c775ceSAlex Deucher 16638cc1a532SAlex Deucher #define CGTS_TCC_DISABLE 0x3c00c 16648cc1a532SAlex Deucher #define CGTS_USER_TCC_DISABLE 0x3c010 16658cc1a532SAlex Deucher #define TCC_DISABLE_MASK 0xFFFF0000 16668cc1a532SAlex Deucher #define TCC_DISABLE_SHIFT 16 16678cc1a532SAlex Deucher 1668f6796caeSAlex Deucher #define CB_CGTT_SCLK_CTRL 0x3c2a0 1669f6796caeSAlex Deucher 1670841cf442SAlex Deucher /* 1671841cf442SAlex Deucher * PM4 1672841cf442SAlex Deucher */ 1673841cf442SAlex Deucher #define PACKET_TYPE0 0 1674841cf442SAlex Deucher #define PACKET_TYPE1 1 1675841cf442SAlex Deucher #define PACKET_TYPE2 2 1676841cf442SAlex Deucher #define PACKET_TYPE3 3 1677841cf442SAlex Deucher 1678841cf442SAlex Deucher #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1679841cf442SAlex Deucher #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1680841cf442SAlex Deucher #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1681841cf442SAlex Deucher #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1682841cf442SAlex Deucher #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1683841cf442SAlex Deucher (((reg) >> 2) & 0xFFFF) | \ 1684841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 1685841cf442SAlex Deucher #define CP_PACKET2 0x80000000 1686841cf442SAlex Deucher #define PACKET2_PAD_SHIFT 0 1687841cf442SAlex Deucher #define PACKET2_PAD_MASK (0x3fffffff << 0) 1688841cf442SAlex Deucher 1689841cf442SAlex Deucher #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1690841cf442SAlex Deucher 1691841cf442SAlex Deucher #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1692841cf442SAlex Deucher (((op) & 0xFF) << 8) | \ 1693841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 1694841cf442SAlex Deucher 1695841cf442SAlex Deucher #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1696841cf442SAlex Deucher 1697841cf442SAlex Deucher /* Packet 3 types */ 1698841cf442SAlex Deucher #define PACKET3_NOP 0x10 1699841cf442SAlex Deucher #define PACKET3_SET_BASE 0x11 1700841cf442SAlex Deucher #define PACKET3_BASE_INDEX(x) ((x) << 0) 1701841cf442SAlex Deucher #define CE_PARTITION_BASE 3 1702841cf442SAlex Deucher #define PACKET3_CLEAR_STATE 0x12 1703841cf442SAlex Deucher #define PACKET3_INDEX_BUFFER_SIZE 0x13 1704841cf442SAlex Deucher #define PACKET3_DISPATCH_DIRECT 0x15 1705841cf442SAlex Deucher #define PACKET3_DISPATCH_INDIRECT 0x16 1706841cf442SAlex Deucher #define PACKET3_ATOMIC_GDS 0x1D 1707841cf442SAlex Deucher #define PACKET3_ATOMIC_MEM 0x1E 1708841cf442SAlex Deucher #define PACKET3_OCCLUSION_QUERY 0x1F 1709841cf442SAlex Deucher #define PACKET3_SET_PREDICATION 0x20 1710841cf442SAlex Deucher #define PACKET3_REG_RMW 0x21 1711841cf442SAlex Deucher #define PACKET3_COND_EXEC 0x22 1712841cf442SAlex Deucher #define PACKET3_PRED_EXEC 0x23 1713841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT 0x24 1714841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1715841cf442SAlex Deucher #define PACKET3_INDEX_BASE 0x26 1716841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_2 0x27 1717841cf442SAlex Deucher #define PACKET3_CONTEXT_CONTROL 0x28 1718841cf442SAlex Deucher #define PACKET3_INDEX_TYPE 0x2A 1719841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1720841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_AUTO 0x2D 1721841cf442SAlex Deucher #define PACKET3_NUM_INSTANCES 0x2F 1722841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1723841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1724841cf442SAlex Deucher #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1725841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1726841cf442SAlex Deucher #define PACKET3_DRAW_PREAMBLE 0x36 1727841cf442SAlex Deucher #define PACKET3_WRITE_DATA 0x37 17282cae3bc3SAlex Deucher #define WRITE_DATA_DST_SEL(x) ((x) << 8) 17292cae3bc3SAlex Deucher /* 0 - register 17302cae3bc3SAlex Deucher * 1 - memory (sync - via GRBM) 17312cae3bc3SAlex Deucher * 2 - gl2 17322cae3bc3SAlex Deucher * 3 - gds 17332cae3bc3SAlex Deucher * 4 - reserved 17342cae3bc3SAlex Deucher * 5 - memory (async - direct) 17352cae3bc3SAlex Deucher */ 17362cae3bc3SAlex Deucher #define WR_ONE_ADDR (1 << 16) 17372cae3bc3SAlex Deucher #define WR_CONFIRM (1 << 20) 17382cae3bc3SAlex Deucher #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 17392cae3bc3SAlex Deucher /* 0 - LRU 17402cae3bc3SAlex Deucher * 1 - Stream 17412cae3bc3SAlex Deucher */ 17422cae3bc3SAlex Deucher #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 17432cae3bc3SAlex Deucher /* 0 - me 17442cae3bc3SAlex Deucher * 1 - pfp 17452cae3bc3SAlex Deucher * 2 - ce 17462cae3bc3SAlex Deucher */ 1747841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1748841cf442SAlex Deucher #define PACKET3_MEM_SEMAPHORE 0x39 17492cae3bc3SAlex Deucher # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 17502cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 17512cae3bc3SAlex Deucher # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 17522cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 17532cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1754841cf442SAlex Deucher #define PACKET3_COPY_DW 0x3B 1755841cf442SAlex Deucher #define PACKET3_WAIT_REG_MEM 0x3C 17562cae3bc3SAlex Deucher #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 17572cae3bc3SAlex Deucher /* 0 - always 17582cae3bc3SAlex Deucher * 1 - < 17592cae3bc3SAlex Deucher * 2 - <= 17602cae3bc3SAlex Deucher * 3 - == 17612cae3bc3SAlex Deucher * 4 - != 17622cae3bc3SAlex Deucher * 5 - >= 17632cae3bc3SAlex Deucher * 6 - > 17642cae3bc3SAlex Deucher */ 17652cae3bc3SAlex Deucher #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 17662cae3bc3SAlex Deucher /* 0 - reg 17672cae3bc3SAlex Deucher * 1 - mem 17682cae3bc3SAlex Deucher */ 17692cae3bc3SAlex Deucher #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 17702cae3bc3SAlex Deucher /* 0 - wait_reg_mem 17712cae3bc3SAlex Deucher * 1 - wr_wait_wr_reg 17722cae3bc3SAlex Deucher */ 17732cae3bc3SAlex Deucher #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 17742cae3bc3SAlex Deucher /* 0 - me 17752cae3bc3SAlex Deucher * 1 - pfp 17762cae3bc3SAlex Deucher */ 1777841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER 0x3F 17782cae3bc3SAlex Deucher #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 17792cae3bc3SAlex Deucher #define INDIRECT_BUFFER_VALID (1 << 23) 17802cae3bc3SAlex Deucher #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 17812cae3bc3SAlex Deucher /* 0 - LRU 17822cae3bc3SAlex Deucher * 1 - Stream 17832cae3bc3SAlex Deucher * 2 - Bypass 17842cae3bc3SAlex Deucher */ 1785841cf442SAlex Deucher #define PACKET3_COPY_DATA 0x40 1786841cf442SAlex Deucher #define PACKET3_PFP_SYNC_ME 0x42 1787841cf442SAlex Deucher #define PACKET3_SURFACE_SYNC 0x43 1788841cf442SAlex Deucher # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1789841cf442SAlex Deucher # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1790841cf442SAlex Deucher # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1791841cf442SAlex Deucher # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1792841cf442SAlex Deucher # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1793841cf442SAlex Deucher # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1794841cf442SAlex Deucher # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1795841cf442SAlex Deucher # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1796841cf442SAlex Deucher # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1797841cf442SAlex Deucher # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1798841cf442SAlex Deucher # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1799841cf442SAlex Deucher # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1800841cf442SAlex Deucher # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1801841cf442SAlex Deucher # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1802841cf442SAlex Deucher # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1803841cf442SAlex Deucher # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1804841cf442SAlex Deucher # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1805841cf442SAlex Deucher # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1806841cf442SAlex Deucher # define PACKET3_CB_ACTION_ENA (1 << 25) 1807841cf442SAlex Deucher # define PACKET3_DB_ACTION_ENA (1 << 26) 1808841cf442SAlex Deucher # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1809841cf442SAlex Deucher # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1810841cf442SAlex Deucher # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1811841cf442SAlex Deucher #define PACKET3_COND_WRITE 0x45 1812841cf442SAlex Deucher #define PACKET3_EVENT_WRITE 0x46 1813841cf442SAlex Deucher #define EVENT_TYPE(x) ((x) << 0) 1814841cf442SAlex Deucher #define EVENT_INDEX(x) ((x) << 8) 1815841cf442SAlex Deucher /* 0 - any non-TS event 1816841cf442SAlex Deucher * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1817841cf442SAlex Deucher * 2 - SAMPLE_PIPELINESTAT 1818841cf442SAlex Deucher * 3 - SAMPLE_STREAMOUTSTAT* 1819841cf442SAlex Deucher * 4 - *S_PARTIAL_FLUSH 1820841cf442SAlex Deucher * 5 - EOP events 1821841cf442SAlex Deucher * 6 - EOS events 1822841cf442SAlex Deucher */ 1823841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOP 0x47 1824841cf442SAlex Deucher #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1825841cf442SAlex Deucher #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1826841cf442SAlex Deucher #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1827841cf442SAlex Deucher #define EOP_TCL1_ACTION_EN (1 << 16) 1828841cf442SAlex Deucher #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 1829b397207bSAlex Deucher #define EOP_TCL2_VOLATILE (1 << 24) 18302cae3bc3SAlex Deucher #define EOP_CACHE_POLICY(x) ((x) << 25) 1831841cf442SAlex Deucher /* 0 - LRU 1832841cf442SAlex Deucher * 1 - Stream 1833841cf442SAlex Deucher * 2 - Bypass 1834841cf442SAlex Deucher */ 1835841cf442SAlex Deucher #define DATA_SEL(x) ((x) << 29) 1836841cf442SAlex Deucher /* 0 - discard 1837841cf442SAlex Deucher * 1 - send low 32bit data 1838841cf442SAlex Deucher * 2 - send 64bit data 1839841cf442SAlex Deucher * 3 - send 64bit GPU counter value 1840841cf442SAlex Deucher * 4 - send 64bit sys counter value 1841841cf442SAlex Deucher */ 1842841cf442SAlex Deucher #define INT_SEL(x) ((x) << 24) 1843841cf442SAlex Deucher /* 0 - none 1844841cf442SAlex Deucher * 1 - interrupt only (DATA_SEL = 0) 1845841cf442SAlex Deucher * 2 - interrupt when data write is confirmed 1846841cf442SAlex Deucher */ 1847841cf442SAlex Deucher #define DST_SEL(x) ((x) << 16) 1848841cf442SAlex Deucher /* 0 - MC 1849841cf442SAlex Deucher * 1 - TC/L2 1850841cf442SAlex Deucher */ 1851841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOS 0x48 1852841cf442SAlex Deucher #define PACKET3_RELEASE_MEM 0x49 1853841cf442SAlex Deucher #define PACKET3_PREAMBLE_CNTL 0x4A 1854841cf442SAlex Deucher # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1855841cf442SAlex Deucher # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1856841cf442SAlex Deucher #define PACKET3_DMA_DATA 0x50 1857c9dbd705SAlex Deucher /* 1. header 1858c9dbd705SAlex Deucher * 2. CONTROL 1859c9dbd705SAlex Deucher * 3. SRC_ADDR_LO or DATA [31:0] 1860c9dbd705SAlex Deucher * 4. SRC_ADDR_HI [31:0] 1861c9dbd705SAlex Deucher * 5. DST_ADDR_LO [31:0] 1862c9dbd705SAlex Deucher * 6. DST_ADDR_HI [7:0] 1863c9dbd705SAlex Deucher * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 1864c9dbd705SAlex Deucher */ 1865c9dbd705SAlex Deucher /* CONTROL */ 1866c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 1867c9dbd705SAlex Deucher /* 0 - ME 1868c9dbd705SAlex Deucher * 1 - PFP 1869c9dbd705SAlex Deucher */ 1870c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 1871c9dbd705SAlex Deucher /* 0 - LRU 1872c9dbd705SAlex Deucher * 1 - Stream 1873c9dbd705SAlex Deucher * 2 - Bypass 1874c9dbd705SAlex Deucher */ 1875c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 1876c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 1877c9dbd705SAlex Deucher /* 0 - DST_ADDR using DAS 1878c9dbd705SAlex Deucher * 1 - GDS 1879c9dbd705SAlex Deucher * 3 - DST_ADDR using L2 1880c9dbd705SAlex Deucher */ 1881c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 1882c9dbd705SAlex Deucher /* 0 - LRU 1883c9dbd705SAlex Deucher * 1 - Stream 1884c9dbd705SAlex Deucher * 2 - Bypass 1885c9dbd705SAlex Deucher */ 1886c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 1887c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 1888c9dbd705SAlex Deucher /* 0 - SRC_ADDR using SAS 1889c9dbd705SAlex Deucher * 1 - GDS 1890c9dbd705SAlex Deucher * 2 - DATA 1891c9dbd705SAlex Deucher * 3 - SRC_ADDR using L2 1892c9dbd705SAlex Deucher */ 1893c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 1894c9dbd705SAlex Deucher /* COMMAND */ 1895c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 1896c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 1897c9dbd705SAlex Deucher /* 0 - none 1898c9dbd705SAlex Deucher * 1 - 8 in 16 1899c9dbd705SAlex Deucher * 2 - 8 in 32 1900c9dbd705SAlex Deucher * 3 - 8 in 64 1901c9dbd705SAlex Deucher */ 1902c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 1903c9dbd705SAlex Deucher /* 0 - none 1904c9dbd705SAlex Deucher * 1 - 8 in 16 1905c9dbd705SAlex Deucher * 2 - 8 in 32 1906c9dbd705SAlex Deucher * 3 - 8 in 64 1907c9dbd705SAlex Deucher */ 1908c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 1909c9dbd705SAlex Deucher /* 0 - memory 1910c9dbd705SAlex Deucher * 1 - register 1911c9dbd705SAlex Deucher */ 1912c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 1913c9dbd705SAlex Deucher /* 0 - memory 1914c9dbd705SAlex Deucher * 1 - register 1915c9dbd705SAlex Deucher */ 1916c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 1917c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 1918c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 1919841cf442SAlex Deucher #define PACKET3_AQUIRE_MEM 0x58 1920841cf442SAlex Deucher #define PACKET3_REWIND 0x59 1921841cf442SAlex Deucher #define PACKET3_LOAD_UCONFIG_REG 0x5E 1922841cf442SAlex Deucher #define PACKET3_LOAD_SH_REG 0x5F 1923841cf442SAlex Deucher #define PACKET3_LOAD_CONFIG_REG 0x60 1924841cf442SAlex Deucher #define PACKET3_LOAD_CONTEXT_REG 0x61 1925841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG 0x68 1926841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_START 0x00008000 1927841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1928841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG 0x69 1929841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1930841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1931841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1932841cf442SAlex Deucher #define PACKET3_SET_SH_REG 0x76 1933841cf442SAlex Deucher #define PACKET3_SET_SH_REG_START 0x0000b000 1934841cf442SAlex Deucher #define PACKET3_SET_SH_REG_END 0x0000c000 1935841cf442SAlex Deucher #define PACKET3_SET_SH_REG_OFFSET 0x77 1936841cf442SAlex Deucher #define PACKET3_SET_QUEUE_REG 0x78 1937841cf442SAlex Deucher #define PACKET3_SET_UCONFIG_REG 0x79 19382cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_START 0x00030000 19392cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1940841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1941841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_READ 0x7E 1942841cf442SAlex Deucher #define PACKET3_LOAD_CONST_RAM 0x80 1943841cf442SAlex Deucher #define PACKET3_WRITE_CONST_RAM 0x81 1944841cf442SAlex Deucher #define PACKET3_DUMP_CONST_RAM 0x83 1945841cf442SAlex Deucher #define PACKET3_INCREMENT_CE_COUNTER 0x84 1946841cf442SAlex Deucher #define PACKET3_INCREMENT_DE_COUNTER 0x85 1947841cf442SAlex Deucher #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1948841cf442SAlex Deucher #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 19492cae3bc3SAlex Deucher #define PACKET3_SWITCH_BUFFER 0x8B 1950841cf442SAlex Deucher 195121a93e13SAlex Deucher /* SDMA - first instance at 0xd000, second at 0xd800 */ 195221a93e13SAlex Deucher #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 195321a93e13SAlex Deucher #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 195421a93e13SAlex Deucher 195521a93e13SAlex Deucher #define SDMA0_UCODE_ADDR 0xD000 195621a93e13SAlex Deucher #define SDMA0_UCODE_DATA 0xD004 195722c775ceSAlex Deucher #define SDMA0_POWER_CNTL 0xD008 195822c775ceSAlex Deucher #define SDMA0_CLK_CTRL 0xD00C 195921a93e13SAlex Deucher 196021a93e13SAlex Deucher #define SDMA0_CNTL 0xD010 196121a93e13SAlex Deucher # define TRAP_ENABLE (1 << 0) 196221a93e13SAlex Deucher # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 196321a93e13SAlex Deucher # define SEM_WAIT_INT_ENABLE (1 << 2) 196421a93e13SAlex Deucher # define DATA_SWAP_ENABLE (1 << 3) 196521a93e13SAlex Deucher # define FENCE_SWAP_ENABLE (1 << 4) 196621a93e13SAlex Deucher # define AUTO_CTXSW_ENABLE (1 << 18) 196721a93e13SAlex Deucher # define CTXEMPTY_INT_ENABLE (1 << 28) 196821a93e13SAlex Deucher 196921a93e13SAlex Deucher #define SDMA0_TILING_CONFIG 0xD018 197021a93e13SAlex Deucher 197121a93e13SAlex Deucher #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 197221a93e13SAlex Deucher #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 197321a93e13SAlex Deucher 197421a93e13SAlex Deucher #define SDMA0_STATUS_REG 0xd034 197521a93e13SAlex Deucher # define SDMA_IDLE (1 << 0) 197621a93e13SAlex Deucher 197721a93e13SAlex Deucher #define SDMA0_ME_CNTL 0xD048 197821a93e13SAlex Deucher # define SDMA_HALT (1 << 0) 197921a93e13SAlex Deucher 198021a93e13SAlex Deucher #define SDMA0_GFX_RB_CNTL 0xD200 198121a93e13SAlex Deucher # define SDMA_RB_ENABLE (1 << 0) 198221a93e13SAlex Deucher # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 198321a93e13SAlex Deucher # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 198421a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 198521a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 198621a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 198721a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE 0xD204 198821a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE_HI 0xD208 198921a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR 0xD20C 199021a93e13SAlex Deucher #define SDMA0_GFX_RB_WPTR 0xD210 199121a93e13SAlex Deucher 199221a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 199321a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 199421a93e13SAlex Deucher #define SDMA0_GFX_IB_CNTL 0xD228 199521a93e13SAlex Deucher # define SDMA_IB_ENABLE (1 << 0) 199621a93e13SAlex Deucher # define SDMA_IB_SWAP_ENABLE (1 << 4) 199721a93e13SAlex Deucher # define SDMA_SWITCH_INSIDE_IB (1 << 8) 199821a93e13SAlex Deucher # define SDMA_CMD_VMID(x) ((x) << 16) 199921a93e13SAlex Deucher 200021a93e13SAlex Deucher #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 200121a93e13SAlex Deucher #define SDMA0_GFX_APE1_CNTL 0xD2A0 200221a93e13SAlex Deucher 200321a93e13SAlex Deucher #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 200421a93e13SAlex Deucher (((sub_op) & 0xFF) << 8) | \ 200521a93e13SAlex Deucher (((op) & 0xFF) << 0)) 200621a93e13SAlex Deucher /* sDMA opcodes */ 200721a93e13SAlex Deucher #define SDMA_OPCODE_NOP 0 200821a93e13SAlex Deucher #define SDMA_OPCODE_COPY 1 200921a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR 0 201021a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED 1 201121a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_SOA 3 201221a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 201321a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 201421a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 201521a93e13SAlex Deucher #define SDMA_OPCODE_WRITE 2 201621a93e13SAlex Deucher # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 2017*6137a0feSGeert Uytterhoeven # define SDMA_WRITE_SUB_OPCODE_TILED 1 201821a93e13SAlex Deucher #define SDMA_OPCODE_INDIRECT_BUFFER 4 201921a93e13SAlex Deucher #define SDMA_OPCODE_FENCE 5 202021a93e13SAlex Deucher #define SDMA_OPCODE_TRAP 6 202121a93e13SAlex Deucher #define SDMA_OPCODE_SEMAPHORE 7 202221a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 202321a93e13SAlex Deucher /* 0 - increment 202421a93e13SAlex Deucher * 1 - write 1 202521a93e13SAlex Deucher */ 202621a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 202721a93e13SAlex Deucher /* 0 - wait 202821a93e13SAlex Deucher * 1 - signal 202921a93e13SAlex Deucher */ 203021a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 203121a93e13SAlex Deucher /* mailbox */ 203221a93e13SAlex Deucher #define SDMA_OPCODE_POLL_REG_MEM 8 203321a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 203421a93e13SAlex Deucher /* 0 - wait_reg_mem 203521a93e13SAlex Deucher * 1 - wr_wait_wr_reg 203621a93e13SAlex Deucher */ 203721a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 203821a93e13SAlex Deucher /* 0 - always 203921a93e13SAlex Deucher * 1 - < 204021a93e13SAlex Deucher * 2 - <= 204121a93e13SAlex Deucher * 3 - == 204221a93e13SAlex Deucher * 4 - != 204321a93e13SAlex Deucher * 5 - >= 204421a93e13SAlex Deucher * 6 - > 204521a93e13SAlex Deucher */ 204621a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 204721a93e13SAlex Deucher /* 0 = register 204821a93e13SAlex Deucher * 1 = memory 204921a93e13SAlex Deucher */ 205021a93e13SAlex Deucher #define SDMA_OPCODE_COND_EXEC 9 205121a93e13SAlex Deucher #define SDMA_OPCODE_CONSTANT_FILL 11 205221a93e13SAlex Deucher # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 205321a93e13SAlex Deucher /* 0 = byte fill 205421a93e13SAlex Deucher * 2 = DW fill 205521a93e13SAlex Deucher */ 205621a93e13SAlex Deucher #define SDMA_OPCODE_GENERATE_PTE_PDE 12 205721a93e13SAlex Deucher #define SDMA_OPCODE_TIMESTAMP 13 205821a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 205921a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 206021a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 206121a93e13SAlex Deucher #define SDMA_OPCODE_SRBM_WRITE 14 206221a93e13SAlex Deucher # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 206321a93e13SAlex Deucher /* byte mask */ 206421a93e13SAlex Deucher 206587167bb1SChristian König /* UVD */ 206687167bb1SChristian König 206787167bb1SChristian König #define UVD_UDEC_ADDR_CONFIG 0xef4c 206887167bb1SChristian König #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 206987167bb1SChristian König #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 207070a033d2SAlex Deucher #define UVD_NO_OP 0xeffc 207187167bb1SChristian König 207287167bb1SChristian König #define UVD_LMI_EXT40_ADDR 0xf498 20738b2cf4f5SArindam Nath #define UVD_GP_SCRATCH4 0xf4e0 207487167bb1SChristian König #define UVD_LMI_ADDR_EXT 0xf594 207587167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET0 0xf608 207687167bb1SChristian König #define UVD_VCPU_CACHE_SIZE0 0xf60c 207787167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET1 0xf610 207887167bb1SChristian König #define UVD_VCPU_CACHE_SIZE1 0xf614 207987167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET2 0xf618 208087167bb1SChristian König #define UVD_VCPU_CACHE_SIZE2 0xf61c 208187167bb1SChristian König 208287167bb1SChristian König #define UVD_RBC_RB_RPTR 0xf690 208387167bb1SChristian König #define UVD_RBC_RB_WPTR 0xf694 208487167bb1SChristian König 208522c775ceSAlex Deucher #define UVD_CGC_CTRL 0xF4B0 208622c775ceSAlex Deucher # define DCM (1 << 0) 208722c775ceSAlex Deucher # define CG_DT(x) ((x) << 2) 208822c775ceSAlex Deucher # define CG_DT_MASK (0xf << 2) 208922c775ceSAlex Deucher # define CLK_OD(x) ((x) << 6) 209022c775ceSAlex Deucher # define CLK_OD_MASK (0x1f << 6) 209122c775ceSAlex Deucher 2092353eec2aSAlex Deucher #define UVD_STATUS 0xf6bc 2093353eec2aSAlex Deucher 209487167bb1SChristian König /* UVD clocks */ 209587167bb1SChristian König 209687167bb1SChristian König #define CG_DCLK_CNTL 0xC050009C 209787167bb1SChristian König # define DCLK_DIVIDER_MASK 0x7f 209887167bb1SChristian König # define DCLK_DIR_CNTL_EN (1 << 8) 209987167bb1SChristian König #define CG_DCLK_STATUS 0xC05000A0 210087167bb1SChristian König # define DCLK_STATUS (1 << 0) 210187167bb1SChristian König #define CG_VCLK_CNTL 0xC05000A4 210287167bb1SChristian König #define CG_VCLK_STATUS 0xC05000A8 210387167bb1SChristian König 210422c775ceSAlex Deucher /* UVD CTX indirect */ 210522c775ceSAlex Deucher #define UVD_CGC_MEM_CTRL 0xC0 210622c775ceSAlex Deucher 2107d93f7937SChristian König /* VCE */ 2108d93f7937SChristian König 2109d93f7937SChristian König #define VCE_VCPU_CACHE_OFFSET0 0x20024 2110d93f7937SChristian König #define VCE_VCPU_CACHE_SIZE0 0x20028 2111d93f7937SChristian König #define VCE_VCPU_CACHE_OFFSET1 0x2002c 2112d93f7937SChristian König #define VCE_VCPU_CACHE_SIZE1 0x20030 2113d93f7937SChristian König #define VCE_VCPU_CACHE_OFFSET2 0x20034 2114d93f7937SChristian König #define VCE_VCPU_CACHE_SIZE2 0x20038 2115d93f7937SChristian König #define VCE_RB_RPTR2 0x20178 2116d93f7937SChristian König #define VCE_RB_WPTR2 0x2017c 2117d93f7937SChristian König #define VCE_RB_RPTR 0x2018c 2118d93f7937SChristian König #define VCE_RB_WPTR 0x20190 2119d93f7937SChristian König #define VCE_CLOCK_GATING_A 0x202f8 2120b9fa1883SAlex Deucher # define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0) 2121b9fa1883SAlex Deucher # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) 2122b9fa1883SAlex Deucher # define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4) 2123b9fa1883SAlex Deucher # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4) 2124b9fa1883SAlex Deucher # define CGC_UENC_WAIT_AWAKE (1 << 18) 2125d93f7937SChristian König #define VCE_CLOCK_GATING_B 0x202fc 2126b9fa1883SAlex Deucher #define VCE_CGTT_CLK_OVERRIDE 0x207a0 2127d93f7937SChristian König #define VCE_UENC_CLOCK_GATING 0x207bc 2128b9fa1883SAlex Deucher # define CLOCK_ON_DELAY_MASK (0xf << 0) 2129b9fa1883SAlex Deucher # define CLOCK_ON_DELAY(x) ((x) << 0) 2130b9fa1883SAlex Deucher # define CLOCK_OFF_DELAY_MASK (0xff << 4) 2131b9fa1883SAlex Deucher # define CLOCK_OFF_DELAY(x) ((x) << 4) 2132d93f7937SChristian König #define VCE_UENC_REG_CLOCK_GATING 0x207c0 2133d93f7937SChristian König #define VCE_SYS_INT_EN 0x21300 2134d93f7937SChristian König # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) 213588f9eae4SChristian König #define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c 2136d93f7937SChristian König #define VCE_LMI_CTRL2 0x21474 2137d93f7937SChristian König #define VCE_LMI_CTRL 0x21498 2138d93f7937SChristian König #define VCE_LMI_VM_CTRL 0x214a0 2139d93f7937SChristian König #define VCE_LMI_SWAP_CNTL 0x214b4 2140d93f7937SChristian König #define VCE_LMI_SWAP_CNTL1 0x214b8 2141d93f7937SChristian König #define VCE_LMI_CACHE_CTRL 0x214f4 2142d93f7937SChristian König 2143d93f7937SChristian König #define VCE_CMD_NO_OP 0x00000000 2144d93f7937SChristian König #define VCE_CMD_END 0x00000001 2145d93f7937SChristian König #define VCE_CMD_IB 0x00000002 2146d93f7937SChristian König #define VCE_CMD_FENCE 0x00000003 2147d93f7937SChristian König #define VCE_CMD_TRAP 0x00000004 2148d93f7937SChristian König #define VCE_CMD_IB_AUTO 0x00000005 2149d93f7937SChristian König #define VCE_CMD_SEMAPHORE 0x00000006 2150d93f7937SChristian König 2151e28740ecSOded Gabbay #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u 2152edad4023SAlexey Skidanov #define ATC_VMID0_PASID_MAPPING 0x339Cu 2153edad4023SAlexey Skidanov #define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF) 2154edad4023SAlexey Skidanov #define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0 2155edad4023SAlexey Skidanov #define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31) 2156edad4023SAlexey Skidanov #define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31 2157e28740ecSOded Gabbay 2158e28740ecSOded Gabbay #define ATC_VM_APERTURE0_CNTL 0x3310u 2159e28740ecSOded Gabbay #define ATS_ACCESS_MODE_NEVER 0 2160e28740ecSOded Gabbay #define ATS_ACCESS_MODE_ALWAYS 1 2161e28740ecSOded Gabbay 2162e28740ecSOded Gabbay #define ATC_VM_APERTURE0_CNTL2 0x3318u 2163e28740ecSOded Gabbay #define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u 2164e28740ecSOded Gabbay #define ATC_VM_APERTURE0_LOW_ADDR 0x3300u 2165e28740ecSOded Gabbay #define ATC_VM_APERTURE1_CNTL 0x3314u 2166e28740ecSOded Gabbay #define ATC_VM_APERTURE1_CNTL2 0x331Cu 2167e28740ecSOded Gabbay #define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu 2168e28740ecSOded Gabbay #define ATC_VM_APERTURE1_LOW_ADDR 0x3304u 2169e28740ecSOded Gabbay 2170fec77bb5SBen Goz #define IH_VMID_0_LUT 0x3D40u 2171fec77bb5SBen Goz 21728cc1a532SAlex Deucher #endif 2173