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/linux/Documentation/core-api/
H A Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v6_7.h34 #define UMC_V6_7_CE_CNT_INIT (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
46 /* R14 bit shift should be considered, double the number */
48 /* The CH4 bit in SOC physical address */
50 /* The C2 bit in SOC physical address */
52 /* The R14 bit in SOC physical address */
53 #define UMC_V6_7_PA_R14_BIT 34
57 /* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
58 * hash bit is only effective when related setting is enabled
61 (((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
62 (((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
67 * The selection between the 400-based or 200-based values for REG_400M
128 #define PLL_EN BIT(12)
143 #define SSCG_EN BIT(11)
145 #define RESET_N_SEL BIT(10)
146 #define PLL_ENABLE_SEL BIT(8)
153 #define PLL_LOCK BIT(0)
156 #define PHY_READY BIT(1)
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/linux/drivers/pinctrl/airoha/
H A Dpinctrl-an7563.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c).
10 * pins 0-27 -> GPIO0-GPIO27 (dedicated GPIO pads)
11 * pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29)
12 * pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31)
13 * pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35)
14 * pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37)
17 * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is
21 #include "airoha-common.h"
24 * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode
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H A Dpinctrl-en7523.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "airoha-common.h"
13 #define GPIO_I2S_MODE_MASK BIT(12)
14 #define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
15 #define GPIO_LAN3_LED1_MODE_MASK BIT(10)
16 #define GPIO_LAN3_LED0_MODE_MASK BIT(9)
17 #define GPIO_LAN2_LED1_MODE_MASK BIT(8)
18 #define GPIO_LAN2_LED0_MODE_MASK BIT(7)
19 #define GPIO_LAN1_LED1_MODE_MASK BIT(6)
20 #define GPIO_LAN1_LED0_MODE_MASK BIT(5)
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H A Dpinctrl-an7581.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include "airoha-common.h"
12 #define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14)
13 #define GPIO_I2C_MASTER_MODE_MODE BIT(13)
14 #define GPIO_I2S_MODE_MASK BIT(12)
15 #define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
16 #define GPIO_LAN3_LED1_MODE_MASK BIT(10)
17 #define GPIO_LAN3_LED0_MODE_MASK BIT(9)
18 #define GPIO_LAN2_LED1_MODE_MASK BIT(8)
19 #define GPIO_LAN2_LED0_MODE_MASK BIT(7)
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H A Dpinctrl-an7583.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include "airoha-common.h"
12 #define GPIO_LAN3_LED1_MODE_MASK BIT(10)
13 #define GPIO_LAN3_LED0_MODE_MASK BIT(9)
14 #define GPIO_LAN2_LED1_MODE_MASK BIT(8)
15 #define GPIO_LAN2_LED0_MODE_MASK BIT(7)
16 #define GPIO_LAN1_LED1_MODE_MASK BIT(6)
17 #define GPIO_LAN1_LED0_MODE_MASK BIT(5)
18 #define GPIO_LAN0_LED1_MODE_MASK BIT(4)
19 #define GPIO_LAN0_LED0_MODE_MASK BIT(3)
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/linux/include/clocksource/
H A Dtimer-ti-dm.h2 * OMAP Dual-Mode Timers
4 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
74 * These registers are offsets from timer->iobase.
90 * These registers are offsets from timer->func_base. The func_base
109 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
115 #define WP_NONE 0 /* no write pending bit */
129 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
130 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
131 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
132 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
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/linux/arch/powerpc/include/uapi/asm/
H A Delf.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
22 #define R_PPC_ADDR32 1 /* 32bit absolute address */
23 #define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
24 #define R_PPC_ADDR16 3 /* 16bit absolute address */
25 #define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
26 #define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
27 #define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
28 #define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
31 #define R_PPC_REL24 10 /* PC relative 26 bit */
32 #define R_PPC_REL14 11 /* PC relative 16 bit */
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H A Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
9 * since we can keep non-volatile in the thread_struct
56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
103 #define PT_ORIG_R3 34
129 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
132 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
138 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
140 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
146 * The transfer totals 34 quadword. Quadwords 0-31 contain the
153 * structures. This also simplifies the implementation of a bi-arch
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/linux/arch/arm/mach-omap2/
H A Dpowerdomain-common.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
8 * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
16 #include "cm-regbits-34xx.h"
17 #include "prm-regbits-34xx.h"
18 #include "prm-regbits-44xx.h"
21 * OMAP3 and OMAP4 specific register bit initialisations
23 * domain but the bit mapping used applies to all of them
62 return -EEXIST; in omap2_pwrdm_get_mem_bank_onstate_mask()
82 return -EEXIST; in omap2_pwrdm_get_mem_bank_retst_mask()
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H A Dcontrol.h2 * arch/arm/mach-omap2/control.h
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
59 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
77 /* 242x-only CONTROL_GENERAL register offsets */
81 /* 243x-only CONTROL_GENERAL register offsets */
82 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
90 /* 24xx-only CONTROL_GENERAL register offsets */
125 /* 34xx-only CONTROL_GENERAL register offsets */
212 /* 34xx PADCONF register offsets */
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H A Dclockdomains3xxx_data.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2008-2011 Texas Instruments, Inc.
6 * Copyright (C) 2008-2010 Nokia Corporation
16 * software-controllable dependencies. Non-software-controllable
19 * The overly-specific dep_bit names are due to a bit name collision
25 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
29 * To-Do List
30 * -> Port the Sleep/Wakeup dependencies for the domains
41 #include "cm-regbits-34xx.h"
42 #include "prm-regbits-34xx.h"
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/linux/lib/crypto/x86/
H A Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
117 # Add reg to mem using reg-mem add and store
165 # Extract w[t-7]
166 MY_VPALIGNR YTMP0, Y_3, Y_2, 8 # YTMP0 = W[-7]
167 # Calculate w[t-16] + w[t-7]
168 vpaddq Y_0, YTMP0, YTMP0 # YTMP0 = W[-7] + W[-16]
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/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dvenc_ipi_msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * enum venc_ipi_msg_id - message id between AP and VPU
17 * (ipi stands for inter-processor interrupt)
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
36 * @reserved: reserved for future use. vpu is running in 32bit. Without
37 * this reserved field, if kernel run in 64bit. this struct size
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
78 * @bs_addr: pointer to output bit stream buffer
79 * @bs_size: bit stream buffer size
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/linux/lib/
H A Dtest_bitops.c1 // SPDX-License-Identifier: GPL-2.0-only
45 {0x0000000300000000, 34},
46 {0x0000000400000000, 34},
64 return -ENOMEM; in test_bitops_startup()
73 time = ktime_get() - time; in test_bitops_startup()
121 pr_err("ERROR: FOUND SET BIT %d\n", bit_set);
139 MODULE_DESCRIPTION("Bit testin
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/linux/drivers/scsi/
H A Dmyrs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
109 } __packed mem_type:5; /* Byte 0 Bits 0-4 */
110 unsigned rsvd:1; /* Byte 0 Bit 5 */
111 unsigned mem_parity:1; /* Byte 0 Bit 6 */
112 unsigned mem_ecc:1; /* Byte 0 Bit 7 */
172 unsigned short bus_speed_mhz; /* Bytes 4-5 */
176 unsigned char rsvd3[7]; /* Bytes 9-15 */
177 unsigned char bus_name[16]; /* Bytes 16-31 */
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H A Dfdomain_isa.c1 // SPDX-License-Identifier: GPL-2.0
35 /* This driver works *ONLY* for Future Domain cards using the TMC-1800,
36 * TMC-18C50, or TMC-18C30 chip. This includes models TMC-1650, 1660, 1670,
37 * and 1680. These are all 16-bit cards.
41 * work with this driver (these TMC-8xx and TMC-9xx boards may work with the
44 * FUTURE DOMAIN CORP. (C) 1986-1988 V4.0I 03/16/88
45 * FUTURE DOMAIN CORP. (C) 1986-1989 V5.0C2/14/89
46 * FUTURE DOMAIN CORP. (C) 1986-1989 V6.0A7/28/89
47 * FUTURE DOMAIN CORP. (C) 1986-1990 V6.0105/31/90
48 * FUTURE DOMAIN CORP. (C) 1986-1990 V6.0209/18/90
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/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
79 * Acquire il->lock before calling this function !
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
87 * NOTE: Acquire il->lock before calling this function !
181 * The first queue used for block-ack aggregation is #7 (4965 only).
182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
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/linux/arch/alpha/include/uapi/asm/
H A Dauxvec.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 value is -1, then the cache doesn't exist. Otherwise:
14 bit 0-3: Cache set-associativity; 0 means fully associative.
15 bit 4-7: Log2 of cacheline size.
16 bit 8-31: Size of the entire cache >> 8.
17 bit 32-63: Reserved.
20 #define AT_L1I_CACHESHAPE 34
/linux/include/dt-bindings/pinctrl/
H A Domap.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2009-2010 Texas Instruments
12 /* 34xx mux mode options for each pin. See TRM for options */
22 /* 24xx/34xx mux bit defines */
27 /* omap3/4/5 specific mux bit defines */
57 #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
74 #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
72 * bit5 - enable pa predistortion - disabled
74 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
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/linux/arch/parisc/math-emu/
H A Dcnv_float.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
10 PA header file -- do not include this header file for non-PA builds.
40 Deposit_dexponent(dest,src_exponent+(DBL_BIAS-SGL_BIAS))
47 ((exponent < (SGL_P - 1)) ? \
50 #define Int_isinexact_to_sgl(int_value) ((int_value << 33 - SGL_EXP_LENGTH) != 0)
53 if (int_value & 1<<(SGL_EXP_LENGTH - 2)) /* round bit */ \
54 if (((int_value << 34 - SGL_EXP_LENGTH) != 0) || Slow(sgl_value)) \
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/linux/drivers/pinctrl/
H A Dpinctrl-loongson2.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
12 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-utils.h"
26 .bit = bitv, \
53 unsigned int bit; member
72 LOONGSON2_PIN(32), LOONGSON2_PIN(33), LOONGSON2_PIN(34), LOONGSON2_PIN(35),
86 32, 33, 34, 35, 36, 37, 38, 39,
91 static const unsigned int can1_pins[] = {34, 35};
188 seq_printf(s, " %s", dev_name(pcdev->dev)); in loongson2_pin_dbg_show()
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