1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> 5 * Author: Markus Gothe <markus.gothe@genexis.eu> 6 */ 7 8 #include "airoha-common.h" 9 10 /* MUX */ 11 #define REG_GPIO_2ND_I2C_MODE 0x0214 12 #define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) 13 #define GPIO_I2C_MASTER_MODE_MODE BIT(13) 14 #define GPIO_I2S_MODE_MASK BIT(12) 15 #define GPIO_I2C_SLAVE_MODE_MODE BIT(11) 16 #define GPIO_LAN3_LED1_MODE_MASK BIT(10) 17 #define GPIO_LAN3_LED0_MODE_MASK BIT(9) 18 #define GPIO_LAN2_LED1_MODE_MASK BIT(8) 19 #define GPIO_LAN2_LED0_MODE_MASK BIT(7) 20 #define GPIO_LAN1_LED1_MODE_MASK BIT(6) 21 #define GPIO_LAN1_LED0_MODE_MASK BIT(5) 22 #define GPIO_LAN0_LED1_MODE_MASK BIT(4) 23 #define GPIO_LAN0_LED0_MODE_MASK BIT(3) 24 #define PON_TOD_1PPS_MODE_MASK BIT(2) 25 #define GSW_TOD_1PPS_MODE_MASK BIT(1) 26 #define GPIO_2ND_I2C_MODE_MASK BIT(0) 27 28 #define REG_GPIO_SPI_CS1_MODE 0x0218 29 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) 30 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) 31 #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) 32 #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) 33 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) 34 #define GPIO_PCM_SPI_MODE_MASK BIT(16) 35 #define GPIO_PCM2_MODE_MASK BIT(13) 36 #define GPIO_PCM1_MODE_MASK BIT(12) 37 #define GPIO_PCM_INT_MODE_MASK BIT(9) 38 #define GPIO_PCM_RESET_MODE_MASK BIT(8) 39 #define GPIO_SPI_QUAD_MODE_MASK BIT(4) 40 #define GPIO_SPI_CS4_MODE_MASK BIT(3) 41 #define GPIO_SPI_CS3_MODE_MASK BIT(2) 42 #define GPIO_SPI_CS2_MODE_MASK BIT(1) 43 #define GPIO_SPI_CS1_MODE_MASK BIT(0) 44 45 #define REG_GPIO_PON_MODE 0x021c 46 #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) 47 #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) 48 #define GPIO_PCIE_RESET2_MASK BIT(12) 49 #define SIPO_RCLK_MODE_MASK BIT(11) 50 #define GPIO_PCIE_RESET1_MASK BIT(10) 51 #define GPIO_PCIE_RESET0_MASK BIT(9) 52 #define GPIO_UART5_MODE_MASK BIT(8) 53 #define GPIO_UART4_MODE_MASK BIT(7) 54 #define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) 55 #define GPIO_HSUART_MODE_MASK BIT(5) 56 #define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) 57 #define GPIO_UART2_MODE_MASK BIT(3) 58 #define GPIO_SIPO_MODE_MASK BIT(2) 59 #define GPIO_EMMC_MODE_MASK BIT(1) 60 #define GPIO_PON_MODE_MASK BIT(0) 61 62 #define REG_NPU_UART_EN 0x0224 63 #define JTAG_UDI_EN_MASK BIT(4) 64 #define JTAG_DFD_EN_MASK BIT(3) 65 66 #define REG_FORCE_GPIO_EN 0x0228 67 #define FORCE_GPIO_EN(n) BIT(n) 68 69 /* LED MAP */ 70 #define REG_LAN_LED0_MAPPING 0x027c 71 #define REG_LAN_LED1_MAPPING 0x0280 72 73 #define LAN4_LED_MAPPING_MASK GENMASK(18, 16) 74 #define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) 75 76 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12) 77 #define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) 78 79 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8) 80 #define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) 81 82 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4) 83 #define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) 84 85 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0) 86 #define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) 87 88 /* CONF */ 89 #define REG_I2C_SDA_E2 0x001c 90 #define SPI_MISO_E2_MASK BIT(14) 91 #define SPI_MOSI_E2_MASK BIT(13) 92 #define SPI_CLK_E2_MASK BIT(12) 93 #define SPI_CS0_E2_MASK BIT(11) 94 #define PCIE2_RESET_E2_MASK BIT(10) 95 #define PCIE1_RESET_E2_MASK BIT(9) 96 #define PCIE0_RESET_E2_MASK BIT(8) 97 #define UART1_RXD_E2_MASK BIT(3) 98 #define UART1_TXD_E2_MASK BIT(2) 99 #define I2C_SCL_E2_MASK BIT(1) 100 #define I2C_SDA_E2_MASK BIT(0) 101 102 #define REG_I2C_SDA_E4 0x0020 103 #define SPI_MISO_E4_MASK BIT(14) 104 #define SPI_MOSI_E4_MASK BIT(13) 105 #define SPI_CLK_E4_MASK BIT(12) 106 #define SPI_CS0_E4_MASK BIT(11) 107 #define PCIE2_RESET_E4_MASK BIT(10) 108 #define PCIE1_RESET_E4_MASK BIT(9) 109 #define PCIE0_RESET_E4_MASK BIT(8) 110 #define UART1_RXD_E4_MASK BIT(3) 111 #define UART1_TXD_E4_MASK BIT(2) 112 #define I2C_SCL_E4_MASK BIT(1) 113 #define I2C_SDA_E4_MASK BIT(0) 114 115 #define REG_GPIO_L_E2 0x0024 116 #define REG_GPIO_L_E4 0x0028 117 #define REG_GPIO_H_E2 0x002c 118 #define REG_GPIO_H_E4 0x0030 119 120 #define REG_I2C_SDA_PU 0x0044 121 #define SPI_MISO_PU_MASK BIT(14) 122 #define SPI_MOSI_PU_MASK BIT(13) 123 #define SPI_CLK_PU_MASK BIT(12) 124 #define SPI_CS0_PU_MASK BIT(11) 125 #define PCIE2_RESET_PU_MASK BIT(10) 126 #define PCIE1_RESET_PU_MASK BIT(9) 127 #define PCIE0_RESET_PU_MASK BIT(8) 128 #define UART1_RXD_PU_MASK BIT(3) 129 #define UART1_TXD_PU_MASK BIT(2) 130 #define I2C_SCL_PU_MASK BIT(1) 131 #define I2C_SDA_PU_MASK BIT(0) 132 133 #define REG_I2C_SDA_PD 0x0048 134 #define SPI_MISO_PD_MASK BIT(14) 135 #define SPI_MOSI_PD_MASK BIT(13) 136 #define SPI_CLK_PD_MASK BIT(12) 137 #define SPI_CS0_PD_MASK BIT(11) 138 #define PCIE2_RESET_PD_MASK BIT(10) 139 #define PCIE1_RESET_PD_MASK BIT(9) 140 #define PCIE0_RESET_PD_MASK BIT(8) 141 #define UART1_RXD_PD_MASK BIT(3) 142 #define UART1_TXD_PD_MASK BIT(2) 143 #define I2C_SCL_PD_MASK BIT(1) 144 #define I2C_SDA_PD_MASK BIT(0) 145 146 #define REG_GPIO_L_PU 0x004c 147 #define REG_GPIO_L_PD 0x0050 148 #define REG_GPIO_H_PU 0x0054 149 #define REG_GPIO_H_PD 0x0058 150 151 #define REG_PCIE_RESET_OD 0x018c 152 #define PCIE2_RESET_OD_MASK BIT(2) 153 #define PCIE1_RESET_OD_MASK BIT(1) 154 #define PCIE0_RESET_OD_MASK BIT(0) 155 156 /* PWM MODE CONF */ 157 #define REG_GPIO_FLASH_MODE_CFG 0x0034 158 #define GPIO15_FLASH_MODE_CFG BIT(15) 159 #define GPIO14_FLASH_MODE_CFG BIT(14) 160 #define GPIO13_FLASH_MODE_CFG BIT(13) 161 #define GPIO12_FLASH_MODE_CFG BIT(12) 162 #define GPIO11_FLASH_MODE_CFG BIT(11) 163 #define GPIO10_FLASH_MODE_CFG BIT(10) 164 #define GPIO9_FLASH_MODE_CFG BIT(9) 165 #define GPIO8_FLASH_MODE_CFG BIT(8) 166 #define GPIO7_FLASH_MODE_CFG BIT(7) 167 #define GPIO6_FLASH_MODE_CFG BIT(6) 168 #define GPIO5_FLASH_MODE_CFG BIT(5) 169 #define GPIO4_FLASH_MODE_CFG BIT(4) 170 #define GPIO3_FLASH_MODE_CFG BIT(3) 171 #define GPIO2_FLASH_MODE_CFG BIT(2) 172 #define GPIO1_FLASH_MODE_CFG BIT(1) 173 #define GPIO0_FLASH_MODE_CFG BIT(0) 174 175 /* PWM MODE CONF EXT */ 176 #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 177 #define GPIO51_FLASH_MODE_CFG BIT(31) 178 #define GPIO50_FLASH_MODE_CFG BIT(30) 179 #define GPIO49_FLASH_MODE_CFG BIT(29) 180 #define GPIO48_FLASH_MODE_CFG BIT(28) 181 #define GPIO47_FLASH_MODE_CFG BIT(27) 182 #define GPIO46_FLASH_MODE_CFG BIT(26) 183 #define GPIO45_FLASH_MODE_CFG BIT(25) 184 #define GPIO44_FLASH_MODE_CFG BIT(24) 185 #define GPIO43_FLASH_MODE_CFG BIT(23) 186 #define GPIO42_FLASH_MODE_CFG BIT(22) 187 #define GPIO41_FLASH_MODE_CFG BIT(21) 188 #define GPIO40_FLASH_MODE_CFG BIT(20) 189 #define GPIO39_FLASH_MODE_CFG BIT(19) 190 #define GPIO38_FLASH_MODE_CFG BIT(18) 191 #define GPIO37_FLASH_MODE_CFG BIT(17) 192 #define GPIO36_FLASH_MODE_CFG BIT(16) 193 #define GPIO31_FLASH_MODE_CFG BIT(15) 194 #define GPIO30_FLASH_MODE_CFG BIT(14) 195 #define GPIO29_FLASH_MODE_CFG BIT(13) 196 #define GPIO28_FLASH_MODE_CFG BIT(12) 197 #define GPIO27_FLASH_MODE_CFG BIT(11) 198 #define GPIO26_FLASH_MODE_CFG BIT(10) 199 #define GPIO25_FLASH_MODE_CFG BIT(9) 200 #define GPIO24_FLASH_MODE_CFG BIT(8) 201 #define GPIO23_FLASH_MODE_CFG BIT(7) 202 #define GPIO22_FLASH_MODE_CFG BIT(6) 203 #define GPIO21_FLASH_MODE_CFG BIT(5) 204 #define GPIO20_FLASH_MODE_CFG BIT(4) 205 #define GPIO19_FLASH_MODE_CFG BIT(3) 206 #define GPIO18_FLASH_MODE_CFG BIT(2) 207 #define GPIO17_FLASH_MODE_CFG BIT(1) 208 #define GPIO16_FLASH_MODE_CFG BIT(0) 209 210 #define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ 211 { \ 212 .name = (gpio), \ 213 .regmap[0] = { \ 214 AIROHA_FUNC_MUX, \ 215 REG_GPIO_PON_MODE, \ 216 (mux_val), \ 217 (mux_val) \ 218 }, \ 219 .regmap_size = 1, \ 220 } 221 222 #define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ 223 { \ 224 .name = (gpio), \ 225 .regmap[0] = { \ 226 AIROHA_FUNC_PWM_EXT_MUX, \ 227 REG_GPIO_FLASH_MODE_CFG_EXT, \ 228 (mux_val), \ 229 0 \ 230 }, \ 231 .regmap[1] = { \ 232 AIROHA_FUNC_MUX, \ 233 REG_GPIO_PON_MODE, \ 234 (smux_val), \ 235 (smux_val) \ 236 }, \ 237 .regmap_size = 2, \ 238 } 239 240 /* PWM */ 241 #define AIROHA_PINCTRL_PWM(gpio, mux_val) \ 242 { \ 243 .name = (gpio), \ 244 .regmap[0] = { \ 245 AIROHA_FUNC_PWM_MUX, \ 246 REG_GPIO_FLASH_MODE_CFG, \ 247 (mux_val), \ 248 (mux_val) \ 249 }, \ 250 .regmap_size = 1, \ 251 } 252 253 #define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ 254 { \ 255 .name = (gpio), \ 256 .regmap[0] = { \ 257 AIROHA_FUNC_PWM_EXT_MUX, \ 258 REG_GPIO_FLASH_MODE_CFG_EXT, \ 259 (mux_val), \ 260 (mux_val) \ 261 }, \ 262 .regmap_size = 1, \ 263 } 264 265 #define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ 266 { \ 267 .name = (gpio), \ 268 .regmap[0] = { \ 269 AIROHA_FUNC_PWM_EXT_MUX, \ 270 REG_GPIO_FLASH_MODE_CFG_EXT, \ 271 (mux_val), \ 272 (mux_val) \ 273 }, \ 274 .regmap[1] = { \ 275 AIROHA_FUNC_MUX, \ 276 REG_GPIO_PON_MODE, \ 277 (smux_val), \ 278 (smux_val) \ 279 }, \ 280 .regmap_size = 2, \ 281 } 282 283 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ 284 { \ 285 .name = (gpio), \ 286 .regmap[0] = { \ 287 AIROHA_FUNC_MUX, \ 288 REG_GPIO_2ND_I2C_MODE, \ 289 (mux_val), \ 290 (mux_val), \ 291 }, \ 292 .regmap[1] = { \ 293 AIROHA_FUNC_MUX, \ 294 REG_LAN_LED0_MAPPING, \ 295 (map_mask), \ 296 (map_val), \ 297 }, \ 298 .regmap_size = 2, \ 299 } 300 301 #define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ 302 { \ 303 .name = (gpio), \ 304 .regmap[0] = { \ 305 AIROHA_FUNC_MUX, \ 306 REG_GPIO_2ND_I2C_MODE, \ 307 (mux_val), \ 308 (mux_val), \ 309 }, \ 310 .regmap[1] = { \ 311 AIROHA_FUNC_MUX, \ 312 REG_LAN_LED1_MAPPING, \ 313 (map_mask), \ 314 (map_val), \ 315 }, \ 316 .regmap_size = 2, \ 317 } 318 319 static struct pinctrl_pin_desc pinctrl_pins[] = { 320 PINCTRL_PIN(0, "uart1_txd"), 321 PINCTRL_PIN(1, "uart1_rxd"), 322 PINCTRL_PIN(2, "i2c_scl"), 323 PINCTRL_PIN(3, "i2c_sda"), 324 PINCTRL_PIN(4, "spi_cs0"), 325 PINCTRL_PIN(5, "spi_clk"), 326 PINCTRL_PIN(6, "spi_mosi"), 327 PINCTRL_PIN(7, "spi_miso"), 328 PINCTRL_PIN(13, "gpio0"), 329 PINCTRL_PIN(14, "gpio1"), 330 PINCTRL_PIN(15, "gpio2"), 331 PINCTRL_PIN(16, "gpio3"), 332 PINCTRL_PIN(17, "gpio4"), 333 PINCTRL_PIN(18, "gpio5"), 334 PINCTRL_PIN(19, "gpio6"), 335 PINCTRL_PIN(20, "gpio7"), 336 PINCTRL_PIN(21, "gpio8"), 337 PINCTRL_PIN(22, "gpio9"), 338 PINCTRL_PIN(23, "gpio10"), 339 PINCTRL_PIN(24, "gpio11"), 340 PINCTRL_PIN(25, "gpio12"), 341 PINCTRL_PIN(26, "gpio13"), 342 PINCTRL_PIN(27, "gpio14"), 343 PINCTRL_PIN(28, "gpio15"), 344 PINCTRL_PIN(29, "gpio16"), 345 PINCTRL_PIN(30, "gpio17"), 346 PINCTRL_PIN(31, "gpio18"), 347 PINCTRL_PIN(32, "gpio19"), 348 PINCTRL_PIN(33, "gpio20"), 349 PINCTRL_PIN(34, "gpio21"), 350 PINCTRL_PIN(35, "gpio22"), 351 PINCTRL_PIN(36, "gpio23"), 352 PINCTRL_PIN(37, "gpio24"), 353 PINCTRL_PIN(38, "gpio25"), 354 PINCTRL_PIN(39, "gpio26"), 355 PINCTRL_PIN(40, "gpio27"), 356 PINCTRL_PIN(41, "gpio28"), 357 PINCTRL_PIN(42, "gpio29"), 358 PINCTRL_PIN(43, "gpio30"), 359 PINCTRL_PIN(44, "gpio31"), 360 PINCTRL_PIN(45, "gpio32"), 361 PINCTRL_PIN(46, "gpio33"), 362 PINCTRL_PIN(47, "gpio34"), 363 PINCTRL_PIN(48, "gpio35"), 364 PINCTRL_PIN(49, "gpio36"), 365 PINCTRL_PIN(50, "gpio37"), 366 PINCTRL_PIN(51, "gpio38"), 367 PINCTRL_PIN(52, "gpio39"), 368 PINCTRL_PIN(53, "gpio40"), 369 PINCTRL_PIN(54, "gpio41"), 370 PINCTRL_PIN(55, "gpio42"), 371 PINCTRL_PIN(56, "gpio43"), 372 PINCTRL_PIN(57, "gpio44"), 373 PINCTRL_PIN(58, "gpio45"), 374 PINCTRL_PIN(59, "gpio46"), 375 PINCTRL_PIN(60, "pcie_reset0"), 376 PINCTRL_PIN(61, "pcie_reset1"), 377 PINCTRL_PIN(62, "pcie_reset2"), 378 }; 379 380 static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; 381 static const int pon_tod_1pps_pins[] = { 46 }; 382 static const int gsw_tod_1pps_pins[] = { 46 }; 383 static const int sipo_pins[] = { 16, 17 }; 384 static const int sipo_rclk_pins[] = { 16, 17, 43 }; 385 static const int mdio_pins[] = { 14, 15 }; 386 static const int uart2_pins[] = { 48, 55 }; 387 static const int uart2_cts_rts_pins[] = { 46, 47 }; 388 static const int hsuart_pins[] = { 28, 29 }; 389 static const int hsuart_cts_rts_pins[] = { 26, 27 }; 390 static const int uart4_pins[] = { 38, 39 }; 391 static const int uart5_pins[] = { 18, 19 }; 392 static const int i2c0_pins[] = { 2, 3 }; 393 static const int i2c1_pins[] = { 14, 15 }; 394 static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; 395 static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; 396 static const int i2s_pins[] = { 26, 27, 28, 29 }; 397 static const int pcm1_pins[] = { 22, 23, 24, 25 }; 398 static const int pcm2_pins[] = { 18, 19, 20, 21 }; 399 static const int spi_quad_pins[] = { 32, 33 }; 400 static const int spi_pins[] = { 4, 5, 6, 7 }; 401 static const int spi_cs1_pins[] = { 34 }; 402 static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; 403 static const int pcm_spi_int_pins[] = { 14 }; 404 static const int pcm_spi_rst_pins[] = { 15 }; 405 static const int pcm_spi_cs1_pins[] = { 43 }; 406 static const int pcm_spi_cs2_pins[] = { 40 }; 407 static const int pcm_spi_cs2_p128_pins[] = { 40 }; 408 static const int pcm_spi_cs2_p156_pins[] = { 40 }; 409 static const int pcm_spi_cs3_pins[] = { 41 }; 410 static const int pcm_spi_cs4_pins[] = { 42 }; 411 static const int emmc_pins[] = { 412 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 413 }; 414 static const int pnand_pins[] = { 415 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 416 }; 417 static const int gpio0_pins[] = { 13 }; 418 static const int gpio1_pins[] = { 14 }; 419 static const int gpio2_pins[] = { 15 }; 420 static const int gpio3_pins[] = { 16 }; 421 static const int gpio4_pins[] = { 17 }; 422 static const int gpio5_pins[] = { 18 }; 423 static const int gpio6_pins[] = { 19 }; 424 static const int gpio7_pins[] = { 20 }; 425 static const int gpio8_pins[] = { 21 }; 426 static const int gpio9_pins[] = { 22 }; 427 static const int gpio10_pins[] = { 23 }; 428 static const int gpio11_pins[] = { 24 }; 429 static const int gpio12_pins[] = { 25 }; 430 static const int gpio13_pins[] = { 26 }; 431 static const int gpio14_pins[] = { 27 }; 432 static const int gpio15_pins[] = { 28 }; 433 static const int gpio16_pins[] = { 29 }; 434 static const int gpio17_pins[] = { 30 }; 435 static const int gpio18_pins[] = { 31 }; 436 static const int gpio19_pins[] = { 32 }; 437 static const int gpio20_pins[] = { 33 }; 438 static const int gpio21_pins[] = { 34 }; 439 static const int gpio22_pins[] = { 35 }; 440 static const int gpio23_pins[] = { 36 }; 441 static const int gpio24_pins[] = { 37 }; 442 static const int gpio25_pins[] = { 38 }; 443 static const int gpio26_pins[] = { 39 }; 444 static const int gpio27_pins[] = { 40 }; 445 static const int gpio28_pins[] = { 41 }; 446 static const int gpio29_pins[] = { 42 }; 447 static const int gpio30_pins[] = { 43 }; 448 static const int gpio31_pins[] = { 44 }; 449 static const int gpio32_pins[] = { 45 }; 450 static const int gpio33_pins[] = { 46 }; 451 static const int gpio34_pins[] = { 47 }; 452 static const int gpio35_pins[] = { 48 }; 453 static const int gpio36_pins[] = { 49 }; 454 static const int gpio37_pins[] = { 50 }; 455 static const int gpio38_pins[] = { 51 }; 456 static const int gpio39_pins[] = { 52 }; 457 static const int gpio40_pins[] = { 53 }; 458 static const int gpio41_pins[] = { 54 }; 459 static const int gpio42_pins[] = { 55 }; 460 static const int gpio43_pins[] = { 56 }; 461 static const int gpio44_pins[] = { 57 }; 462 static const int gpio45_pins[] = { 58 }; 463 static const int gpio46_pins[] = { 59 }; 464 static const int gpio47_pins[] = { 60 }; 465 static const int gpio48_pins[] = { 61 }; 466 static const int gpio49_pins[] = { 62 }; 467 static const int pcie_reset0_pins[] = { 60 }; 468 static const int pcie_reset1_pins[] = { 61 }; 469 static const int pcie_reset2_pins[] = { 62 }; 470 471 static const struct pingroup pinctrl_groups[] = { 472 PINCTRL_PIN_GROUP("pon", pon), 473 PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), 474 PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), 475 PINCTRL_PIN_GROUP("sipo", sipo), 476 PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), 477 PINCTRL_PIN_GROUP("mdio", mdio), 478 PINCTRL_PIN_GROUP("uart2", uart2), 479 PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), 480 PINCTRL_PIN_GROUP("hsuart", hsuart), 481 PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), 482 PINCTRL_PIN_GROUP("uart4", uart4), 483 PINCTRL_PIN_GROUP("uart5", uart5), 484 PINCTRL_PIN_GROUP("i2c0", i2c0), 485 PINCTRL_PIN_GROUP("i2c1", i2c1), 486 PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), 487 PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), 488 PINCTRL_PIN_GROUP("i2s", i2s), 489 PINCTRL_PIN_GROUP("pcm1", pcm1), 490 PINCTRL_PIN_GROUP("pcm2", pcm2), 491 PINCTRL_PIN_GROUP("spi", spi), 492 PINCTRL_PIN_GROUP("spi_quad", spi_quad), 493 PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), 494 PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), 495 PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), 496 PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), 497 PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), 498 PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), 499 PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), 500 PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), 501 PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), 502 PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), 503 PINCTRL_PIN_GROUP("emmc", emmc), 504 PINCTRL_PIN_GROUP("pnand", pnand), 505 PINCTRL_PIN_GROUP("gpio0", gpio0), 506 PINCTRL_PIN_GROUP("gpio1", gpio1), 507 PINCTRL_PIN_GROUP("gpio2", gpio2), 508 PINCTRL_PIN_GROUP("gpio3", gpio3), 509 PINCTRL_PIN_GROUP("gpio4", gpio4), 510 PINCTRL_PIN_GROUP("gpio5", gpio5), 511 PINCTRL_PIN_GROUP("gpio6", gpio6), 512 PINCTRL_PIN_GROUP("gpio7", gpio7), 513 PINCTRL_PIN_GROUP("gpio8", gpio8), 514 PINCTRL_PIN_GROUP("gpio9", gpio9), 515 PINCTRL_PIN_GROUP("gpio10", gpio10), 516 PINCTRL_PIN_GROUP("gpio11", gpio11), 517 PINCTRL_PIN_GROUP("gpio12", gpio12), 518 PINCTRL_PIN_GROUP("gpio13", gpio13), 519 PINCTRL_PIN_GROUP("gpio14", gpio14), 520 PINCTRL_PIN_GROUP("gpio15", gpio15), 521 PINCTRL_PIN_GROUP("gpio16", gpio16), 522 PINCTRL_PIN_GROUP("gpio17", gpio17), 523 PINCTRL_PIN_GROUP("gpio18", gpio18), 524 PINCTRL_PIN_GROUP("gpio19", gpio19), 525 PINCTRL_PIN_GROUP("gpio20", gpio20), 526 PINCTRL_PIN_GROUP("gpio21", gpio21), 527 PINCTRL_PIN_GROUP("gpio22", gpio22), 528 PINCTRL_PIN_GROUP("gpio23", gpio23), 529 PINCTRL_PIN_GROUP("gpio24", gpio24), 530 PINCTRL_PIN_GROUP("gpio25", gpio25), 531 PINCTRL_PIN_GROUP("gpio26", gpio26), 532 PINCTRL_PIN_GROUP("gpio27", gpio27), 533 PINCTRL_PIN_GROUP("gpio28", gpio28), 534 PINCTRL_PIN_GROUP("gpio29", gpio29), 535 PINCTRL_PIN_GROUP("gpio30", gpio30), 536 PINCTRL_PIN_GROUP("gpio31", gpio31), 537 PINCTRL_PIN_GROUP("gpio32", gpio32), 538 PINCTRL_PIN_GROUP("gpio33", gpio33), 539 PINCTRL_PIN_GROUP("gpio34", gpio34), 540 PINCTRL_PIN_GROUP("gpio35", gpio35), 541 PINCTRL_PIN_GROUP("gpio36", gpio36), 542 PINCTRL_PIN_GROUP("gpio37", gpio37), 543 PINCTRL_PIN_GROUP("gpio38", gpio38), 544 PINCTRL_PIN_GROUP("gpio39", gpio39), 545 PINCTRL_PIN_GROUP("gpio40", gpio40), 546 PINCTRL_PIN_GROUP("gpio41", gpio41), 547 PINCTRL_PIN_GROUP("gpio42", gpio42), 548 PINCTRL_PIN_GROUP("gpio43", gpio43), 549 PINCTRL_PIN_GROUP("gpio44", gpio44), 550 PINCTRL_PIN_GROUP("gpio45", gpio45), 551 PINCTRL_PIN_GROUP("gpio46", gpio46), 552 PINCTRL_PIN_GROUP("gpio47", gpio47), 553 PINCTRL_PIN_GROUP("gpio48", gpio48), 554 PINCTRL_PIN_GROUP("gpio49", gpio49), 555 PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), 556 PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), 557 PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2), 558 }; 559 560 static const char *const pon_groups[] = { "pon" }; 561 static const char *const tod_1pps_groups[] = { 562 "pon_tod_1pps", "gsw_tod_1pps" 563 }; 564 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; 565 static const char *const mdio_groups[] = { "mdio" }; 566 static const char *const uart_groups[] = { 567 "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", 568 "uart4", "uart5" 569 }; 570 static const char *const i2c_groups[] = { "i2c1" }; 571 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; 572 static const char *const pcm_groups[] = { "pcm1", "pcm2" }; 573 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; 574 static const char *const pcm_spi_groups[] = { 575 "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", 576 "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", 577 "pcm_spi_cs4" 578 }; 579 static const char *const i2s_groups[] = { "i2s" }; 580 static const char *const emmc_groups[] = { "emmc" }; 581 static const char *const pnand_groups[] = { "pnand" }; 582 static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; 583 static const char *const pcie_reset_groups[] = { 584 "pcie_reset0", "pcie_reset1", "pcie_reset2" 585 }; 586 static const char *const pwm_groups[] = { 587 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 588 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 589 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 590 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 591 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 592 "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", 593 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", 594 "gpio46", "gpio47", "gpio48", "gpio49" 595 }; 596 static const char *const phy1_led0_groups[] = { 597 "gpio33", "gpio34", "gpio35", "gpio42" 598 }; 599 static const char *const phy2_led0_groups[] = { 600 "gpio33", "gpio34", "gpio35", "gpio42" 601 }; 602 static const char *const phy3_led0_groups[] = { 603 "gpio33", "gpio34", "gpio35", "gpio42" 604 }; 605 static const char *const phy4_led0_groups[] = { 606 "gpio33", "gpio34", "gpio35", "gpio42" 607 }; 608 static const char *const phy1_led1_groups[] = { 609 "gpio43", "gpio44", "gpio45", "gpio46" 610 }; 611 static const char *const phy2_led1_groups[] = { 612 "gpio43", "gpio44", "gpio45", "gpio46" 613 }; 614 static const char *const phy3_led1_groups[] = { 615 "gpio43", "gpio44", "gpio45", "gpio46" 616 }; 617 static const char *const phy4_led1_groups[] = { 618 "gpio43", "gpio44", "gpio45", "gpio46" 619 }; 620 621 static const struct airoha_pinctrl_func_group pon_func_group[] = { 622 { 623 .name = "pon", 624 .regmap[0] = { 625 AIROHA_FUNC_MUX, 626 REG_GPIO_PON_MODE, 627 GPIO_PON_MODE_MASK, 628 GPIO_PON_MODE_MASK 629 }, 630 .regmap_size = 1, 631 }, 632 }; 633 634 static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { 635 { 636 .name = "pon_tod_1pps", 637 .regmap[0] = { 638 AIROHA_FUNC_MUX, 639 REG_GPIO_2ND_I2C_MODE, 640 PON_TOD_1PPS_MODE_MASK, 641 PON_TOD_1PPS_MODE_MASK 642 }, 643 .regmap_size = 1, 644 }, { 645 .name = "gsw_tod_1pps", 646 .regmap[0] = { 647 AIROHA_FUNC_MUX, 648 REG_GPIO_2ND_I2C_MODE, 649 GSW_TOD_1PPS_MODE_MASK, 650 GSW_TOD_1PPS_MODE_MASK 651 }, 652 .regmap_size = 1, 653 }, 654 }; 655 656 static const struct airoha_pinctrl_func_group sipo_func_group[] = { 657 { 658 .name = "sipo", 659 .regmap[0] = { 660 AIROHA_FUNC_MUX, 661 REG_GPIO_PON_MODE, 662 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 663 GPIO_SIPO_MODE_MASK 664 }, 665 .regmap_size = 1, 666 }, { 667 .name = "sipo_rclk", 668 .regmap[0] = { 669 AIROHA_FUNC_MUX, 670 REG_GPIO_PON_MODE, 671 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 672 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK 673 }, 674 .regmap_size = 1, 675 }, 676 }; 677 678 static const struct airoha_pinctrl_func_group mdio_func_group[] = { 679 { 680 .name = "mdio", 681 .regmap[0] = { 682 AIROHA_FUNC_MUX, 683 REG_GPIO_2ND_I2C_MODE, 684 GPIO_MDC_IO_MASTER_MODE_MASK, 685 GPIO_MDC_IO_MASTER_MODE_MASK 686 }, 687 .regmap[1] = { 688 AIROHA_FUNC_MUX, 689 REG_FORCE_GPIO_EN, 690 FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), 691 FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) 692 }, 693 .regmap_size = 2, 694 }, 695 }; 696 697 static const struct airoha_pinctrl_func_group uart_func_group[] = { 698 { 699 .name = "uart2", 700 .regmap[0] = { 701 AIROHA_FUNC_MUX, 702 REG_GPIO_PON_MODE, 703 GPIO_UART2_MODE_MASK, 704 GPIO_UART2_MODE_MASK 705 }, 706 .regmap_size = 1, 707 }, { 708 .name = "uart2_cts_rts", 709 .regmap[0] = { 710 AIROHA_FUNC_MUX, 711 REG_GPIO_PON_MODE, 712 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, 713 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK 714 }, 715 .regmap_size = 1, 716 }, { 717 .name = "hsuart", 718 .regmap[0] = { 719 AIROHA_FUNC_MUX, 720 REG_GPIO_PON_MODE, 721 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 722 GPIO_HSUART_MODE_MASK 723 }, 724 .regmap_size = 1, 725 }, 726 { 727 .name = "hsuart_cts_rts", 728 .regmap[0] = { 729 AIROHA_FUNC_MUX, 730 REG_GPIO_PON_MODE, 731 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 732 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK 733 }, 734 .regmap_size = 1, 735 }, { 736 .name = "uart4", 737 .regmap[0] = { 738 AIROHA_FUNC_MUX, 739 REG_GPIO_PON_MODE, 740 GPIO_UART4_MODE_MASK, 741 GPIO_UART4_MODE_MASK 742 }, 743 .regmap_size = 1, 744 }, { 745 .name = "uart5", 746 .regmap[0] = { 747 AIROHA_FUNC_MUX, 748 REG_GPIO_PON_MODE, 749 GPIO_UART5_MODE_MASK, 750 GPIO_UART5_MODE_MASK 751 }, 752 .regmap_size = 1, 753 }, 754 }; 755 756 static const struct airoha_pinctrl_func_group i2c_func_group[] = { 757 { 758 .name = "i2c1", 759 .regmap[0] = { 760 AIROHA_FUNC_MUX, 761 REG_GPIO_2ND_I2C_MODE, 762 GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, 763 GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE 764 }, 765 .regmap_size = 1, 766 }, 767 }; 768 769 static const struct airoha_pinctrl_func_group jtag_func_group[] = { 770 { 771 .name = "jtag_udi", 772 .regmap[0] = { 773 AIROHA_FUNC_MUX, 774 REG_NPU_UART_EN, 775 JTAG_UDI_EN_MASK, 776 JTAG_UDI_EN_MASK 777 }, 778 .regmap_size = 1, 779 }, { 780 .name = "jtag_dfd", 781 .regmap[0] = { 782 AIROHA_FUNC_MUX, 783 REG_NPU_UART_EN, 784 JTAG_DFD_EN_MASK, 785 JTAG_DFD_EN_MASK 786 }, 787 .regmap_size = 1, 788 }, 789 }; 790 791 static const struct airoha_pinctrl_func_group pcm_func_group[] = { 792 { 793 .name = "pcm1", 794 .regmap[0] = { 795 AIROHA_FUNC_MUX, 796 REG_GPIO_SPI_CS1_MODE, 797 GPIO_PCM1_MODE_MASK, 798 GPIO_PCM1_MODE_MASK 799 }, 800 .regmap_size = 1, 801 }, { 802 .name = "pcm2", 803 .regmap[0] = { 804 AIROHA_FUNC_MUX, 805 REG_GPIO_SPI_CS1_MODE, 806 GPIO_PCM2_MODE_MASK, 807 GPIO_PCM2_MODE_MASK 808 }, 809 .regmap_size = 1, 810 }, 811 }; 812 813 static const struct airoha_pinctrl_func_group spi_func_group[] = { 814 { 815 .name = "spi_quad", 816 .regmap[0] = { 817 AIROHA_FUNC_MUX, 818 REG_GPIO_SPI_CS1_MODE, 819 GPIO_SPI_QUAD_MODE_MASK, 820 GPIO_SPI_QUAD_MODE_MASK 821 }, 822 .regmap_size = 1, 823 }, { 824 .name = "spi_cs1", 825 .regmap[0] = { 826 AIROHA_FUNC_MUX, 827 REG_GPIO_SPI_CS1_MODE, 828 GPIO_SPI_CS1_MODE_MASK, 829 GPIO_SPI_CS1_MODE_MASK 830 }, 831 .regmap_size = 1, 832 }, { 833 .name = "spi_cs2", 834 .regmap[0] = { 835 AIROHA_FUNC_MUX, 836 REG_GPIO_SPI_CS1_MODE, 837 GPIO_SPI_CS2_MODE_MASK, 838 GPIO_SPI_CS2_MODE_MASK 839 }, 840 .regmap_size = 1, 841 }, { 842 .name = "spi_cs3", 843 .regmap[0] = { 844 AIROHA_FUNC_MUX, 845 REG_GPIO_SPI_CS1_MODE, 846 GPIO_SPI_CS3_MODE_MASK, 847 GPIO_SPI_CS3_MODE_MASK 848 }, 849 .regmap_size = 1, 850 }, { 851 .name = "spi_cs4", 852 .regmap[0] = { 853 AIROHA_FUNC_MUX, 854 REG_GPIO_SPI_CS1_MODE, 855 GPIO_SPI_CS4_MODE_MASK, 856 GPIO_SPI_CS4_MODE_MASK 857 }, 858 .regmap_size = 1, 859 }, 860 }; 861 862 static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { 863 { 864 .name = "pcm_spi", 865 .regmap[0] = { 866 AIROHA_FUNC_MUX, 867 REG_GPIO_SPI_CS1_MODE, 868 GPIO_PCM_SPI_MODE_MASK, 869 GPIO_PCM_SPI_MODE_MASK 870 }, 871 .regmap_size = 1, 872 }, { 873 .name = "pcm_spi_int", 874 .regmap[0] = { 875 AIROHA_FUNC_MUX, 876 REG_GPIO_SPI_CS1_MODE, 877 GPIO_PCM_INT_MODE_MASK, 878 GPIO_PCM_INT_MODE_MASK 879 }, 880 .regmap_size = 1, 881 }, { 882 .name = "pcm_spi_rst", 883 .regmap[0] = { 884 AIROHA_FUNC_MUX, 885 REG_GPIO_SPI_CS1_MODE, 886 GPIO_PCM_RESET_MODE_MASK, 887 GPIO_PCM_RESET_MODE_MASK 888 }, 889 .regmap_size = 1, 890 }, { 891 .name = "pcm_spi_cs1", 892 .regmap[0] = { 893 AIROHA_FUNC_MUX, 894 REG_GPIO_SPI_CS1_MODE, 895 GPIO_PCM_SPI_CS1_MODE_MASK, 896 GPIO_PCM_SPI_CS1_MODE_MASK 897 }, 898 .regmap_size = 1, 899 }, { 900 .name = "pcm_spi_cs2_p128", 901 .regmap[0] = { 902 AIROHA_FUNC_MUX, 903 REG_GPIO_SPI_CS1_MODE, 904 GPIO_PCM_SPI_CS2_MODE_P128_MASK, 905 GPIO_PCM_SPI_CS2_MODE_P128_MASK 906 }, 907 .regmap_size = 1, 908 }, { 909 .name = "pcm_spi_cs2_p156", 910 .regmap[0] = { 911 AIROHA_FUNC_MUX, 912 REG_GPIO_SPI_CS1_MODE, 913 GPIO_PCM_SPI_CS2_MODE_P156_MASK, 914 GPIO_PCM_SPI_CS2_MODE_P156_MASK 915 }, 916 .regmap_size = 1, 917 }, { 918 .name = "pcm_spi_cs3", 919 .regmap[0] = { 920 AIROHA_FUNC_MUX, 921 REG_GPIO_SPI_CS1_MODE, 922 GPIO_PCM_SPI_CS3_MODE_MASK, 923 GPIO_PCM_SPI_CS3_MODE_MASK 924 }, 925 .regmap_size = 1, 926 }, { 927 .name = "pcm_spi_cs4", 928 .regmap[0] = { 929 AIROHA_FUNC_MUX, 930 REG_GPIO_SPI_CS1_MODE, 931 GPIO_PCM_SPI_CS4_MODE_MASK, 932 GPIO_PCM_SPI_CS4_MODE_MASK 933 }, 934 .regmap_size = 1, 935 }, 936 }; 937 938 static const struct airoha_pinctrl_func_group i2s_func_group[] = { 939 { 940 .name = "i2s", 941 .regmap[0] = { 942 AIROHA_FUNC_MUX, 943 REG_GPIO_2ND_I2C_MODE, 944 GPIO_I2S_MODE_MASK, 945 GPIO_I2S_MODE_MASK 946 }, 947 .regmap_size = 1, 948 }, 949 }; 950 951 static const struct airoha_pinctrl_func_group emmc_func_group[] = { 952 { 953 .name = "emmc", 954 .regmap[0] = { 955 AIROHA_FUNC_MUX, 956 REG_GPIO_PON_MODE, 957 GPIO_EMMC_MODE_MASK, 958 GPIO_EMMC_MODE_MASK 959 }, 960 .regmap_size = 1, 961 }, 962 }; 963 964 static const struct airoha_pinctrl_func_group pnand_func_group[] = { 965 { 966 .name = "pnand", 967 .regmap[0] = { 968 AIROHA_FUNC_MUX, 969 REG_GPIO_PON_MODE, 970 GPIO_PARALLEL_NAND_MODE_MASK, 971 GPIO_PARALLEL_NAND_MODE_MASK 972 }, 973 .regmap_size = 1, 974 }, 975 }; 976 977 static const struct airoha_pinctrl_func_group gpio_func_group[] = { 978 AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, 979 GPIO_PCIE_RESET0_MASK), 980 AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, 981 GPIO_PCIE_RESET1_MASK), 982 AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, 983 GPIO_PCIE_RESET2_MASK), 984 }; 985 986 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { 987 { 988 .name = "pcie_reset0", 989 .regmap[0] = { 990 AIROHA_FUNC_MUX, 991 REG_GPIO_PON_MODE, 992 GPIO_PCIE_RESET0_MASK, 993 0 994 }, 995 .regmap_size = 1, 996 }, { 997 .name = "pcie_reset1", 998 .regmap[0] = { 999 AIROHA_FUNC_MUX, 1000 REG_GPIO_PON_MODE, 1001 GPIO_PCIE_RESET1_MASK, 1002 0 1003 }, 1004 .regmap_size = 1, 1005 }, { 1006 .name = "pcie_reset2", 1007 .regmap[0] = { 1008 AIROHA_FUNC_MUX, 1009 REG_GPIO_PON_MODE, 1010 GPIO_PCIE_RESET2_MASK, 1011 0 1012 }, 1013 .regmap_size = 1, 1014 }, 1015 }; 1016 1017 static const struct airoha_pinctrl_func_group pwm_func_group[] = { 1018 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), 1019 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), 1020 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), 1021 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), 1022 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), 1023 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), 1024 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), 1025 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), 1026 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), 1027 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), 1028 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), 1029 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), 1030 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), 1031 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), 1032 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), 1033 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), 1034 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), 1035 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), 1036 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), 1037 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), 1038 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), 1039 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), 1040 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), 1041 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), 1042 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), 1043 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), 1044 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), 1045 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), 1046 AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), 1047 AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), 1048 AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), 1049 AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), 1050 AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), 1051 AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), 1052 AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), 1053 AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), 1054 AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), 1055 AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), 1056 AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), 1057 AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), 1058 AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), 1059 AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), 1060 AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), 1061 AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, 1062 GPIO_PCIE_RESET0_MASK), 1063 AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, 1064 GPIO_PCIE_RESET1_MASK), 1065 AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, 1066 GPIO_PCIE_RESET2_MASK), 1067 }; 1068 1069 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { 1070 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1071 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1072 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1073 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1074 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1075 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1076 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1077 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1078 }; 1079 1080 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { 1081 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1082 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1083 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1084 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1085 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1086 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1087 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1088 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1089 }; 1090 1091 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { 1092 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1093 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1094 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1095 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1096 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1097 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1098 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1099 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1100 }; 1101 1102 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { 1103 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1104 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1105 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1106 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1107 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1108 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1109 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1110 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1111 }; 1112 1113 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { 1114 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1115 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1116 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1117 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1118 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1119 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1120 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1121 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1122 }; 1123 1124 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { 1125 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1126 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1127 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1128 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1129 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1130 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1131 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1132 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1133 }; 1134 1135 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { 1136 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1137 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1138 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1139 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1140 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1141 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1142 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1143 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1144 }; 1145 1146 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { 1147 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1148 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1149 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1150 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1151 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1152 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1153 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1154 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1155 }; 1156 1157 static const struct airoha_pinctrl_func pinctrl_funcs[] = { 1158 PINCTRL_FUNC_DESC("pon", pon), 1159 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), 1160 PINCTRL_FUNC_DESC("sipo", sipo), 1161 PINCTRL_FUNC_DESC("mdio", mdio), 1162 PINCTRL_FUNC_DESC("uart", uart), 1163 PINCTRL_FUNC_DESC("i2c", i2c), 1164 PINCTRL_FUNC_DESC("jtag", jtag), 1165 PINCTRL_FUNC_DESC("pcm", pcm), 1166 PINCTRL_FUNC_DESC("spi", spi), 1167 PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), 1168 PINCTRL_FUNC_DESC("i2s", i2s), 1169 PINCTRL_FUNC_DESC("emmc", emmc), 1170 PINCTRL_FUNC_DESC("pnand", pnand), 1171 PINCTRL_FUNC_DESC("gpio", gpio), 1172 PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), 1173 PINCTRL_FUNC_DESC("pwm", pwm), 1174 PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), 1175 PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), 1176 PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), 1177 PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), 1178 PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), 1179 PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), 1180 PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), 1181 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), 1182 }; 1183 1184 static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { 1185 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 1186 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 1187 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 1188 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 1189 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 1190 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 1191 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 1192 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 1193 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), 1194 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), 1195 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), 1196 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), 1197 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), 1198 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), 1199 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), 1200 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), 1201 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), 1202 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), 1203 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), 1204 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), 1205 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), 1206 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), 1207 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), 1208 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), 1209 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), 1210 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), 1211 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), 1212 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), 1213 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), 1214 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), 1215 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), 1216 PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), 1217 PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), 1218 PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), 1219 PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), 1220 PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), 1221 PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), 1222 PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), 1223 PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), 1224 PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), 1225 PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), 1226 PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), 1227 PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), 1228 PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), 1229 PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), 1230 PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), 1231 PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), 1232 PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), 1233 PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), 1234 PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), 1235 PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), 1236 PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), 1237 PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), 1238 PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), 1239 PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), 1240 PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 1241 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 1242 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), 1243 }; 1244 1245 static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { 1246 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 1247 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 1248 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 1249 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 1250 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 1251 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 1252 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 1253 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 1254 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), 1255 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), 1256 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), 1257 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), 1258 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), 1259 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), 1260 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), 1261 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), 1262 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), 1263 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), 1264 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), 1265 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), 1266 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), 1267 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), 1268 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), 1269 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), 1270 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), 1271 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), 1272 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), 1273 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), 1274 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), 1275 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), 1276 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), 1277 PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), 1278 PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), 1279 PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), 1280 PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), 1281 PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), 1282 PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), 1283 PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), 1284 PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), 1285 PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), 1286 PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), 1287 PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), 1288 PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), 1289 PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), 1290 PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), 1291 PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), 1292 PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), 1293 PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), 1294 PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), 1295 PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), 1296 PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), 1297 PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), 1298 PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), 1299 PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), 1300 PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), 1301 PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 1302 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 1303 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), 1304 }; 1305 1306 static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { 1307 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 1308 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 1309 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 1310 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 1311 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 1312 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 1313 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 1314 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 1315 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), 1316 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), 1317 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), 1318 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), 1319 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), 1320 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), 1321 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), 1322 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), 1323 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), 1324 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), 1325 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), 1326 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), 1327 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), 1328 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), 1329 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), 1330 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), 1331 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), 1332 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), 1333 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), 1334 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), 1335 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), 1336 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), 1337 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), 1338 PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), 1339 PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), 1340 PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), 1341 PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), 1342 PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), 1343 PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), 1344 PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), 1345 PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), 1346 PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), 1347 PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), 1348 PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), 1349 PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), 1350 PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), 1351 PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), 1352 PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), 1353 PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), 1354 PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), 1355 PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), 1356 PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), 1357 PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), 1358 PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), 1359 PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), 1360 PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), 1361 PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), 1362 PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 1363 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 1364 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), 1365 }; 1366 1367 static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { 1368 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 1369 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 1370 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 1371 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 1372 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 1373 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 1374 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 1375 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 1376 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), 1377 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), 1378 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), 1379 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), 1380 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), 1381 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), 1382 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), 1383 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), 1384 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), 1385 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), 1386 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), 1387 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), 1388 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), 1389 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), 1390 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), 1391 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), 1392 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), 1393 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), 1394 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), 1395 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), 1396 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), 1397 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), 1398 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), 1399 PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), 1400 PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), 1401 PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), 1402 PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), 1403 PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), 1404 PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), 1405 PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), 1406 PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), 1407 PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), 1408 PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), 1409 PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), 1410 PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), 1411 PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), 1412 PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), 1413 PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), 1414 PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), 1415 PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), 1416 PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), 1417 PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), 1418 PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), 1419 PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), 1420 PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), 1421 PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), 1422 PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), 1423 PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 1424 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 1425 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), 1426 }; 1427 1428 static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { 1429 PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), 1430 PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), 1431 PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), 1432 }; 1433 1434 static const struct airoha_pinctrl_match_data pinctrl_match_data = { 1435 .chip_scu_compatible = "airoha,en7581-chip-scu", 1436 .pinctrl_name = KBUILD_MODNAME, 1437 .pinctrl_owner = THIS_MODULE, 1438 .pins = pinctrl_pins, 1439 .num_pins = ARRAY_SIZE(pinctrl_pins), 1440 .grps = pinctrl_groups, 1441 .num_grps = ARRAY_SIZE(pinctrl_groups), 1442 .funcs = pinctrl_funcs, 1443 .num_funcs = ARRAY_SIZE(pinctrl_funcs), 1444 .confs_info = { 1445 [AIROHA_PINCTRL_CONFS_PULLUP] = { 1446 .confs = pinctrl_pullup_conf, 1447 .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), 1448 }, 1449 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 1450 .confs = pinctrl_pulldown_conf, 1451 .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), 1452 }, 1453 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 1454 .confs = pinctrl_drive_e2_conf, 1455 .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), 1456 }, 1457 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 1458 .confs = pinctrl_drive_e4_conf, 1459 .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), 1460 }, 1461 [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { 1462 .confs = pinctrl_pcie_rst_od_conf, 1463 .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), 1464 }, 1465 }, 1466 }; 1467 1468 static const struct of_device_id airoha_pinctrl_of_match[] = { 1469 { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data }, 1470 { /* sentinel */ } 1471 }; 1472 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); 1473 1474 static struct platform_driver airoha_pinctrl_driver = { 1475 .probe = airoha_pinctrl_probe, 1476 .driver = { 1477 .name = "pinctrl-airoha-an7581", 1478 .of_match_table = airoha_pinctrl_of_match, 1479 }, 1480 }; 1481 module_platform_driver(airoha_pinctrl_driver); 1482 1483 MODULE_LICENSE("GPL"); 1484 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 1485 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); 1486 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); 1487 MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC"); 1488