1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c). 4 * 5 * Sources: AN7563 Programming Guide chapter 2 (CHIP SCU, base 0x1fa20000), 6 * chapter 17 (GPIO controller, base 0x1fbf0200) and AN7563PT datasheet 7 * chapter 4.3 (pin sharing scheme). 8 * 9 * Pin numbering follows the GPIO line numbering of the SoC: 10 * pins 0-27 -> GPIO0-GPIO27 (dedicated GPIO pads) 11 * pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29) 12 * pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31) 13 * pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35) 14 * pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37) 15 * 16 * Definitions marked "shared" are identical to the ones already present in 17 * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is 18 * merged there. 19 */ 20 21 #include "airoha-common.h" 22 23 /* 24 * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode 25 * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS). 26 */ 27 #define REG_GPIO_2ND_I2C_MODE 0x0214 28 #define GPIO_LAN3_LED1_MODE_MASK BIT(10) 29 #define GPIO_LAN3_LED0_MODE_MASK BIT(9) 30 #define GPIO_LAN2_LED1_MODE_MASK BIT(8) 31 #define GPIO_LAN2_LED0_MODE_MASK BIT(7) 32 #define GPIO_LAN1_LED1_MODE_MASK BIT(6) 33 #define GPIO_LAN1_LED0_MODE_MASK BIT(5) 34 #define GPIO_LAN0_LED1_MODE_MASK BIT(4) 35 #define GPIO_LAN0_LED0_MODE_MASK BIT(3) 36 #define GSW_TOD_1PPS_MODE_MASK BIT(1) 37 38 /* shared */ 39 #define REG_GPIO_SPI_CS1_MODE 0x0218 40 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) 41 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) 42 #define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) 43 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) 44 #define GPIO_PCM_SPI_MODE_MASK BIT(16) 45 #define GPIO_PCM2_MODE_MASK BIT(13) 46 #define GPIO_PCM1_MODE_MASK BIT(12) 47 #define GPIO_PCM_INT_MODE_MASK BIT(9) 48 #define GPIO_PCM_RESET_MODE_MASK BIT(8) 49 #define GPIO_SPI_QUAD_MODE_MASK BIT(4) 50 #define GPIO_SPI_CS4_MODE_MASK BIT(3) 51 #define GPIO_SPI_CS3_MODE_MASK BIT(2) 52 #define GPIO_SPI_CS2_MODE_MASK BIT(1) 53 #define GPIO_SPI_CS1_MODE_MASK BIT(0) 54 55 #define REG_GPIO_PON_MODE 0x021c 56 /* 57 * AN7563 specific: route the standalone pads to their GPIO function. 58 * 0: pad keeps its base function, 1: pad is GPIO<n>. 59 */ 60 #define UART_RXD_GPIO_MODE_MASK BIT(22) /* GPIO37 */ 61 #define UART_TXD_GPIO_MODE_MASK BIT(21) /* GPIO36 */ 62 #define SPI_MISO_GPIO_MODE_MASK BIT(20) /* GPIO35 */ 63 #define SPI_MOSI_GPIO_MODE_MASK BIT(19) /* GPIO34 */ 64 #define SPI_CS_GPIO_MODE_MASK BIT(18) /* GPIO33 */ 65 #define SPI_CLK_GPIO_MODE_MASK BIT(17) /* GPIO32 */ 66 #define I2C_SDA_GPIO_MODE_MASK BIT(16) /* GPIO31 */ 67 #define I2C_SCL_GPIO_MODE_MASK BIT(15) /* GPIO30 */ 68 /* shared */ 69 #define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) 70 #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) 71 #define SIPO_RCLK_MODE_MASK BIT(11) 72 /* 73 * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the 74 * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29). 75 */ 76 #define GPIO_PCIE_RESET1_MASK BIT(10) /* GPIO29 */ 77 #define GPIO_PCIE_RESET0_MASK BIT(9) /* GPIO28 */ 78 #define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) 79 #define GPIO_HSUART_MODE_MASK BIT(5) 80 #define GPIO_SIPO_MODE_MASK BIT(2) 81 #define GPIO_PON_MODE_MASK BIT(0) 82 83 /* shared */ 84 #define REG_NPU_UART_EN 0x0224 85 #define JTAG_UDI_EN_MASK BIT(4) 86 #define JTAG_DFD_EN_MASK BIT(3) 87 88 /* LED MAP - shared */ 89 #define REG_LAN_LED0_MAPPING 0x027c 90 #define REG_LAN_LED1_MAPPING 0x0280 91 92 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12) 93 #define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) 94 95 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8) 96 #define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) 97 98 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4) 99 #define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) 100 101 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0) 102 #define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) 103 104 /* 105 * CONF - shared. 106 * The AN7563 standalone IO conf registers use the same bit layout as 107 * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563). 108 */ 109 #define REG_I2C_SDA_E2 0x001c 110 #define SPI_MISO_E2_MASK BIT(14) 111 #define SPI_MOSI_E2_MASK BIT(13) 112 #define SPI_CLK_E2_MASK BIT(12) 113 #define SPI_CS0_E2_MASK BIT(11) 114 #define PCIE1_RESET_E2_MASK BIT(9) 115 #define PCIE0_RESET_E2_MASK BIT(8) 116 #define UART1_RXD_E2_MASK BIT(3) 117 #define UART1_TXD_E2_MASK BIT(2) 118 #define I2C_SCL_E2_MASK BIT(1) 119 #define I2C_SDA_E2_MASK BIT(0) 120 121 #define REG_I2C_SDA_E4 0x0020 122 #define SPI_MISO_E4_MASK BIT(14) 123 #define SPI_MOSI_E4_MASK BIT(13) 124 #define SPI_CLK_E4_MASK BIT(12) 125 #define SPI_CS0_E4_MASK BIT(11) 126 #define PCIE1_RESET_E4_MASK BIT(9) 127 #define PCIE0_RESET_E4_MASK BIT(8) 128 #define UART1_RXD_E4_MASK BIT(3) 129 #define UART1_TXD_E4_MASK BIT(2) 130 #define I2C_SCL_E4_MASK BIT(1) 131 #define I2C_SDA_E4_MASK BIT(0) 132 133 #define REG_GPIO_L_E2 0x0024 134 #define REG_GPIO_L_E4 0x0028 135 136 #define REG_I2C_SDA_PU 0x0044 137 #define SPI_MISO_PU_MASK BIT(14) 138 #define SPI_MOSI_PU_MASK BIT(13) 139 #define SPI_CLK_PU_MASK BIT(12) 140 #define SPI_CS0_PU_MASK BIT(11) 141 #define PCIE1_RESET_PU_MASK BIT(9) 142 #define PCIE0_RESET_PU_MASK BIT(8) 143 #define UART1_RXD_PU_MASK BIT(3) 144 #define UART1_TXD_PU_MASK BIT(2) 145 #define I2C_SCL_PU_MASK BIT(1) 146 #define I2C_SDA_PU_MASK BIT(0) 147 148 #define REG_I2C_SDA_PD 0x0048 149 #define SPI_MISO_PD_MASK BIT(14) 150 #define SPI_MOSI_PD_MASK BIT(13) 151 #define SPI_CLK_PD_MASK BIT(12) 152 #define SPI_CS0_PD_MASK BIT(11) 153 #define PCIE1_RESET_PD_MASK BIT(9) 154 #define PCIE0_RESET_PD_MASK BIT(8) 155 #define UART1_RXD_PD_MASK BIT(3) 156 #define UART1_TXD_PD_MASK BIT(2) 157 #define I2C_SCL_PD_MASK BIT(1) 158 #define I2C_SDA_PD_MASK BIT(0) 159 160 #define REG_GPIO_L_PU 0x004c 161 #define REG_GPIO_L_PD 0x0050 162 163 #define REG_PCIE_RESET_OD 0x018c 164 #define PCIE1_RESET_OD_MASK BIT(1) 165 #define PCIE0_RESET_OD_MASK BIT(0) 166 167 /* 168 * PWM MODE CONF - shared. 169 * The AN7563 GPIO flash mode registers use the same layout as EN7581: 170 * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT 171 * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads 172 * (GPIO32-35) have no flash mode configuration bit. 173 */ 174 #define REG_GPIO_FLASH_MODE_CFG 0x0034 175 #define GPIO15_FLASH_MODE_CFG BIT(15) 176 #define GPIO14_FLASH_MODE_CFG BIT(14) 177 #define GPIO13_FLASH_MODE_CFG BIT(13) 178 #define GPIO12_FLASH_MODE_CFG BIT(12) 179 #define GPIO11_FLASH_MODE_CFG BIT(11) 180 #define GPIO10_FLASH_MODE_CFG BIT(10) 181 #define GPIO9_FLASH_MODE_CFG BIT(9) 182 #define GPIO8_FLASH_MODE_CFG BIT(8) 183 #define GPIO7_FLASH_MODE_CFG BIT(7) 184 #define GPIO6_FLASH_MODE_CFG BIT(6) 185 #define GPIO5_FLASH_MODE_CFG BIT(5) 186 #define GPIO4_FLASH_MODE_CFG BIT(4) 187 #define GPIO3_FLASH_MODE_CFG BIT(3) 188 #define GPIO2_FLASH_MODE_CFG BIT(2) 189 #define GPIO1_FLASH_MODE_CFG BIT(1) 190 #define GPIO0_FLASH_MODE_CFG BIT(0) 191 192 #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 193 #define GPIO37_FLASH_MODE_CFG BIT(17) 194 #define GPIO36_FLASH_MODE_CFG BIT(16) 195 #define GPIO31_FLASH_MODE_CFG BIT(15) 196 #define GPIO30_FLASH_MODE_CFG BIT(14) 197 #define GPIO29_FLASH_MODE_CFG BIT(13) 198 #define GPIO28_FLASH_MODE_CFG BIT(12) 199 #define GPIO27_FLASH_MODE_CFG BIT(11) 200 #define GPIO26_FLASH_MODE_CFG BIT(10) 201 #define GPIO25_FLASH_MODE_CFG BIT(9) 202 #define GPIO24_FLASH_MODE_CFG BIT(8) 203 #define GPIO23_FLASH_MODE_CFG BIT(7) 204 #define GPIO22_FLASH_MODE_CFG BIT(6) 205 #define GPIO21_FLASH_MODE_CFG BIT(5) 206 #define GPIO20_FLASH_MODE_CFG BIT(4) 207 #define GPIO19_FLASH_MODE_CFG BIT(3) 208 #define GPIO18_FLASH_MODE_CFG BIT(2) 209 #define GPIO17_FLASH_MODE_CFG BIT(1) 210 #define GPIO16_FLASH_MODE_CFG BIT(0) 211 212 #define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ 213 { \ 214 .name = (gpio), \ 215 .regmap[0] = { \ 216 AIROHA_FUNC_MUX, \ 217 REG_GPIO_PON_MODE, \ 218 (mux_val), \ 219 (mux_val) \ 220 }, \ 221 .regmap_size = 1, \ 222 } 223 224 #define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ 225 { \ 226 .name = (gpio), \ 227 .regmap[0] = { \ 228 AIROHA_FUNC_PWM_EXT_MUX, \ 229 REG_GPIO_FLASH_MODE_CFG_EXT, \ 230 (mux_val), \ 231 0 \ 232 }, \ 233 .regmap[1] = { \ 234 AIROHA_FUNC_MUX, \ 235 REG_GPIO_PON_MODE, \ 236 (smux_val), \ 237 (smux_val) \ 238 }, \ 239 .regmap_size = 2, \ 240 } 241 242 /* PWM */ 243 #define AIROHA_PINCTRL_PWM(gpio, mux_val) \ 244 { \ 245 .name = (gpio), \ 246 .regmap[0] = { \ 247 AIROHA_FUNC_PWM_MUX, \ 248 REG_GPIO_FLASH_MODE_CFG, \ 249 (mux_val), \ 250 (mux_val) \ 251 }, \ 252 .regmap_size = 1, \ 253 } 254 255 #define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ 256 { \ 257 .name = (gpio), \ 258 .regmap[0] = { \ 259 AIROHA_FUNC_PWM_EXT_MUX, \ 260 REG_GPIO_FLASH_MODE_CFG_EXT, \ 261 (mux_val), \ 262 (mux_val) \ 263 }, \ 264 .regmap_size = 1, \ 265 } 266 267 #define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ 268 { \ 269 .name = (gpio), \ 270 .regmap[0] = { \ 271 AIROHA_FUNC_PWM_EXT_MUX, \ 272 REG_GPIO_FLASH_MODE_CFG_EXT, \ 273 (mux_val), \ 274 (mux_val) \ 275 }, \ 276 .regmap[1] = { \ 277 AIROHA_FUNC_MUX, \ 278 REG_GPIO_PON_MODE, \ 279 (smux_val), \ 280 (smux_val) \ 281 }, \ 282 .regmap_size = 2, \ 283 } 284 285 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ 286 { \ 287 .name = (gpio), \ 288 .regmap[0] = { \ 289 AIROHA_FUNC_MUX, \ 290 REG_GPIO_2ND_I2C_MODE, \ 291 (mux_val), \ 292 (mux_val), \ 293 }, \ 294 .regmap[1] = { \ 295 AIROHA_FUNC_MUX, \ 296 REG_LAN_LED0_MAPPING, \ 297 (map_mask), \ 298 (map_val), \ 299 }, \ 300 .regmap_size = 2, \ 301 } 302 303 #define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ 304 { \ 305 .name = (gpio), \ 306 .regmap[0] = { \ 307 AIROHA_FUNC_MUX, \ 308 REG_GPIO_2ND_I2C_MODE, \ 309 (mux_val), \ 310 (mux_val), \ 311 }, \ 312 .regmap[1] = { \ 313 AIROHA_FUNC_MUX, \ 314 REG_LAN_LED1_MAPPING, \ 315 (map_mask), \ 316 (map_val), \ 317 }, \ 318 .regmap_size = 2, \ 319 } 320 321 static const struct pinctrl_pin_desc pinctrl_pins[] = { 322 PINCTRL_PIN(0, "gpio0"), 323 PINCTRL_PIN(1, "gpio1"), 324 PINCTRL_PIN(2, "gpio2"), 325 PINCTRL_PIN(3, "gpio3"), 326 PINCTRL_PIN(4, "gpio4"), 327 PINCTRL_PIN(5, "gpio5"), 328 PINCTRL_PIN(6, "gpio6"), 329 PINCTRL_PIN(7, "gpio7"), 330 PINCTRL_PIN(8, "gpio8"), 331 PINCTRL_PIN(9, "gpio9"), 332 PINCTRL_PIN(10, "gpio10"), 333 PINCTRL_PIN(11, "gpio11"), 334 PINCTRL_PIN(12, "gpio12"), 335 PINCTRL_PIN(13, "gpio13"), 336 PINCTRL_PIN(14, "gpio14"), 337 PINCTRL_PIN(15, "gpio15"), 338 PINCTRL_PIN(16, "gpio16"), 339 PINCTRL_PIN(17, "gpio17"), 340 PINCTRL_PIN(18, "gpio18"), 341 PINCTRL_PIN(19, "gpio19"), 342 PINCTRL_PIN(20, "gpio20"), 343 PINCTRL_PIN(21, "gpio21"), 344 PINCTRL_PIN(22, "gpio22"), 345 PINCTRL_PIN(23, "gpio23"), 346 PINCTRL_PIN(24, "gpio24"), 347 PINCTRL_PIN(25, "gpio25"), 348 PINCTRL_PIN(26, "gpio26"), 349 PINCTRL_PIN(27, "gpio27"), 350 PINCTRL_PIN(28, "pcie_reset0"), /* GPIO28 */ 351 PINCTRL_PIN(29, "pcie_reset1"), /* GPIO29 */ 352 PINCTRL_PIN(30, "i2c_scl"), /* GPIO30 */ 353 PINCTRL_PIN(31, "i2c_sda"), /* GPIO31 */ 354 PINCTRL_PIN(32, "spi_clk"), /* GPIO32 */ 355 PINCTRL_PIN(33, "spi_cs"), /* GPIO33 */ 356 PINCTRL_PIN(34, "spi_mosi"), /* GPIO34 */ 357 PINCTRL_PIN(35, "spi_miso"), /* GPIO35 */ 358 PINCTRL_PIN(36, "uart_txd"), /* GPIO36 */ 359 PINCTRL_PIN(37, "uart_rxd"), /* GPIO37 */ 360 }; 361 362 static const int pon_pins[] = { 14, 15, 16, 17, 18, 19 }; 363 static const int sipo_pins[] = { 20, 21 }; 364 static const int sipo_rclk_pins[] = { 20, 21, 26 }; 365 static const int mdio_pins[] = { 30, 31 }; 366 static const int hsuart_pins[] = { 16, 17 }; 367 static const int hsuart_cts_rts_pins[] = { 14, 15 }; 368 static const int i2c_pins[] = { 30, 31 }; 369 static const int jtag_udi_pins[] = { 7, 8, 9, 10, 11 }; 370 static const int jtag_dfd_pins[] = { 7, 8, 9, 10, 11 }; 371 static const int pcm1_pins[] = { 22, 23, 24, 25 }; 372 static const int pcm2_pins[] = { 1, 2, 3, 4 }; 373 static const int spi_pins[] = { 32, 33, 34, 35 }; 374 static const int spi_quad_pins[] = { 2, 3 }; 375 static const int spi_cs1_pins[] = { 4 }; 376 static const int pnand_pins[] = { 377 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 33, 34, 35 378 }; 379 static const int gpio0_pins[] = { 0 }; 380 static const int gpio1_pins[] = { 1 }; 381 static const int gpio2_pins[] = { 2 }; 382 static const int gpio3_pins[] = { 3 }; 383 static const int gpio4_pins[] = { 4 }; 384 static const int gpio5_pins[] = { 5 }; 385 static const int gpio6_pins[] = { 6 }; 386 static const int gpio7_pins[] = { 7 }; 387 static const int gpio8_pins[] = { 8 }; 388 static const int gpio9_pins[] = { 9 }; 389 static const int gpio10_pins[] = { 10 }; 390 static const int gpio11_pins[] = { 11 }; 391 static const int gpio12_pins[] = { 12 }; 392 static const int gpio13_pins[] = { 13 }; 393 static const int gpio14_pins[] = { 14 }; 394 static const int gpio15_pins[] = { 15 }; 395 static const int gpio16_pins[] = { 16 }; 396 static const int gpio17_pins[] = { 17 }; 397 static const int gpio18_pins[] = { 18 }; 398 static const int gpio19_pins[] = { 19 }; 399 static const int gpio20_pins[] = { 20 }; 400 static const int gpio21_pins[] = { 21 }; 401 static const int gpio22_pins[] = { 22 }; 402 static const int gpio23_pins[] = { 23 }; 403 static const int gpio24_pins[] = { 24 }; 404 static const int gpio25_pins[] = { 25 }; 405 static const int gpio26_pins[] = { 26 }; 406 static const int gpio27_pins[] = { 27 }; 407 static const int gpio28_pins[] = { 28 }; 408 static const int gpio29_pins[] = { 29 }; 409 static const int gpio30_pins[] = { 30 }; 410 static const int gpio31_pins[] = { 31 }; 411 static const int gpio32_pins[] = { 32 }; 412 static const int gpio33_pins[] = { 33 }; 413 static const int gpio34_pins[] = { 34 }; 414 static const int gpio35_pins[] = { 35 }; 415 static const int gpio36_pins[] = { 36 }; 416 static const int gpio37_pins[] = { 37 }; 417 static const int pcie_reset0_pins[] = { 28 }; 418 static const int pcie_reset1_pins[] = { 29 }; 419 420 static const struct pingroup pinctrl_groups[] = { 421 PINCTRL_PIN_GROUP("pon", pon), 422 PINCTRL_PIN_GROUP("sipo", sipo), 423 PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), 424 PINCTRL_PIN_GROUP("mdio", mdio), 425 PINCTRL_PIN_GROUP("hsuart", hsuart), 426 PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), 427 PINCTRL_PIN_GROUP("i2c", i2c), 428 PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), 429 PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), 430 PINCTRL_PIN_GROUP("pcm1", pcm1), 431 PINCTRL_PIN_GROUP("pcm2", pcm2), 432 PINCTRL_PIN_GROUP("spi", spi), 433 PINCTRL_PIN_GROUP("spi_quad", spi_quad), 434 PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), 435 PINCTRL_PIN_GROUP("pnand", pnand), 436 PINCTRL_PIN_GROUP("gpio0", gpio0), 437 PINCTRL_PIN_GROUP("gpio1", gpio1), 438 PINCTRL_PIN_GROUP("gpio2", gpio2), 439 PINCTRL_PIN_GROUP("gpio3", gpio3), 440 PINCTRL_PIN_GROUP("gpio4", gpio4), 441 PINCTRL_PIN_GROUP("gpio5", gpio5), 442 PINCTRL_PIN_GROUP("gpio6", gpio6), 443 PINCTRL_PIN_GROUP("gpio7", gpio7), 444 PINCTRL_PIN_GROUP("gpio8", gpio8), 445 PINCTRL_PIN_GROUP("gpio9", gpio9), 446 PINCTRL_PIN_GROUP("gpio10", gpio10), 447 PINCTRL_PIN_GROUP("gpio11", gpio11), 448 PINCTRL_PIN_GROUP("gpio12", gpio12), 449 PINCTRL_PIN_GROUP("gpio13", gpio13), 450 PINCTRL_PIN_GROUP("gpio14", gpio14), 451 PINCTRL_PIN_GROUP("gpio15", gpio15), 452 PINCTRL_PIN_GROUP("gpio16", gpio16), 453 PINCTRL_PIN_GROUP("gpio17", gpio17), 454 PINCTRL_PIN_GROUP("gpio18", gpio18), 455 PINCTRL_PIN_GROUP("gpio19", gpio19), 456 PINCTRL_PIN_GROUP("gpio20", gpio20), 457 PINCTRL_PIN_GROUP("gpio21", gpio21), 458 PINCTRL_PIN_GROUP("gpio22", gpio22), 459 PINCTRL_PIN_GROUP("gpio23", gpio23), 460 PINCTRL_PIN_GROUP("gpio24", gpio24), 461 PINCTRL_PIN_GROUP("gpio25", gpio25), 462 PINCTRL_PIN_GROUP("gpio26", gpio26), 463 PINCTRL_PIN_GROUP("gpio27", gpio27), 464 PINCTRL_PIN_GROUP("gpio28", gpio28), 465 PINCTRL_PIN_GROUP("gpio29", gpio29), 466 PINCTRL_PIN_GROUP("gpio30", gpio30), 467 PINCTRL_PIN_GROUP("gpio31", gpio31), 468 PINCTRL_PIN_GROUP("gpio32", gpio32), 469 PINCTRL_PIN_GROUP("gpio33", gpio33), 470 PINCTRL_PIN_GROUP("gpio34", gpio34), 471 PINCTRL_PIN_GROUP("gpio35", gpio35), 472 PINCTRL_PIN_GROUP("gpio36", gpio36), 473 PINCTRL_PIN_GROUP("gpio37", gpio37), 474 PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), 475 PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), 476 }; 477 478 /* shared */ 479 static const char *const pon_groups[] = { "pon" }; 480 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; 481 static const char *const mdio_groups[] = { "mdio" }; 482 static const char *const uart_groups[] = { 483 "hsuart", "hsuart_cts_rts" 484 }; 485 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; 486 static const char *const pcm_groups[] = { "pcm1", "pcm2" }; 487 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; 488 static const char *const pnand_groups[] = { "pnand" }; 489 static const char *const gpio_groups[] = { 490 "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", 491 "gpio33", "gpio34", "gpio35", "gpio36", "gpio37" 492 }; 493 static const char *const pcie_reset_groups[] = { 494 "pcie_reset0", "pcie_reset1" 495 }; 496 static const char *const pwm_groups[] = { 497 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 498 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 499 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 500 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 501 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 502 "gpio30", "gpio31", "gpio36", "gpio37" 503 }; 504 static const char *const phy1_led0_groups[] = { 505 "gpio8", "gpio9", "gpio10", "gpio11" 506 }; 507 static const char *const phy2_led0_groups[] = { 508 "gpio8", "gpio9", "gpio10", "gpio11" 509 }; 510 static const char *const phy3_led0_groups[] = { 511 "gpio8", "gpio9", "gpio10", "gpio11" 512 }; 513 static const char *const phy4_led0_groups[] = { 514 "gpio8", "gpio9", "gpio10", "gpio11" 515 }; 516 static const char *const phy1_led1_groups[] = { 517 "gpio4", "gpio5", "gpio6", "gpio7" 518 }; 519 static const char *const phy2_led1_groups[] = { 520 "gpio4", "gpio5", "gpio6", "gpio7" 521 }; 522 static const char *const phy3_led1_groups[] = { 523 "gpio4", "gpio5", "gpio6", "gpio7" 524 }; 525 static const char *const phy4_led1_groups[] = { 526 "gpio4", "gpio5", "gpio6", "gpio7" 527 }; 528 529 /* shared */ 530 static const struct airoha_pinctrl_func_group pon_func_group[] = { 531 { 532 .name = "pon", 533 .regmap[0] = { 534 AIROHA_FUNC_MUX, 535 REG_GPIO_PON_MODE, 536 GPIO_PON_MODE_MASK, 537 GPIO_PON_MODE_MASK 538 }, 539 .regmap_size = 1, 540 }, 541 }; 542 543 /* shared */ 544 static const struct airoha_pinctrl_func_group sipo_func_group[] = { 545 { 546 .name = "sipo", 547 .regmap[0] = { 548 AIROHA_FUNC_MUX, 549 REG_GPIO_PON_MODE, 550 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 551 GPIO_SIPO_MODE_MASK 552 }, 553 .regmap_size = 1, 554 }, { 555 .name = "sipo_rclk", 556 .regmap[0] = { 557 AIROHA_FUNC_MUX, 558 REG_GPIO_PON_MODE, 559 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 560 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK 561 }, 562 .regmap_size = 1, 563 }, 564 }; 565 566 /* 567 * On AN7563 the SMI master (MDC/MDIO) is shared with the I2C_SCL/I2C_SDA 568 * pads and selected via the SGMII MDIO mode bit. I2C is the default pad 569 * function (no mux bit). 570 */ 571 static const struct airoha_pinctrl_func_group mdio_func_group[] = { 572 { 573 .name = "mdio", 574 .regmap[0] = { 575 AIROHA_FUNC_MUX, 576 REG_GPIO_PON_MODE, 577 GPIO_SGMII_MDIO_MODE_MASK, 578 GPIO_SGMII_MDIO_MODE_MASK 579 }, 580 .regmap_size = 1, 581 }, 582 }; 583 584 static const struct airoha_pinctrl_func_group uart_func_group[] = { 585 { 586 .name = "hsuart", 587 .regmap[0] = { 588 AIROHA_FUNC_MUX, 589 REG_GPIO_PON_MODE, 590 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 591 GPIO_HSUART_MODE_MASK 592 }, 593 .regmap_size = 1, 594 }, 595 { 596 .name = "hsuart_cts_rts", 597 .regmap[0] = { 598 AIROHA_FUNC_MUX, 599 REG_GPIO_PON_MODE, 600 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 601 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK 602 }, 603 .regmap_size = 1, 604 }, 605 }; 606 607 /* shared */ 608 static const struct airoha_pinctrl_func_group jtag_func_group[] = { 609 { 610 .name = "jtag_udi", 611 .regmap[0] = { 612 AIROHA_FUNC_MUX, 613 REG_NPU_UART_EN, 614 JTAG_UDI_EN_MASK, 615 JTAG_UDI_EN_MASK 616 }, 617 .regmap_size = 1, 618 }, { 619 .name = "jtag_dfd", 620 .regmap[0] = { 621 AIROHA_FUNC_MUX, 622 REG_NPU_UART_EN, 623 JTAG_DFD_EN_MASK, 624 JTAG_DFD_EN_MASK 625 }, 626 .regmap_size = 1, 627 }, 628 }; 629 630 /* shared */ 631 static const struct airoha_pinctrl_func_group pcm_func_group[] = { 632 { 633 .name = "pcm1", 634 .regmap[0] = { 635 AIROHA_FUNC_MUX, 636 REG_GPIO_SPI_CS1_MODE, 637 GPIO_PCM1_MODE_MASK, 638 GPIO_PCM1_MODE_MASK 639 }, 640 .regmap_size = 1, 641 }, { 642 .name = "pcm2", 643 .regmap[0] = { 644 AIROHA_FUNC_MUX, 645 REG_GPIO_SPI_CS1_MODE, 646 GPIO_PCM2_MODE_MASK, 647 GPIO_PCM2_MODE_MASK 648 }, 649 .regmap_size = 1, 650 }, 651 }; 652 653 /* shared */ 654 static const struct airoha_pinctrl_func_group spi_func_group[] = { 655 { 656 .name = "spi_quad", 657 .regmap[0] = { 658 AIROHA_FUNC_MUX, 659 REG_GPIO_SPI_CS1_MODE, 660 GPIO_SPI_QUAD_MODE_MASK, 661 GPIO_SPI_QUAD_MODE_MASK 662 }, 663 .regmap_size = 1, 664 }, { 665 .name = "spi_cs1", 666 .regmap[0] = { 667 AIROHA_FUNC_MUX, 668 REG_GPIO_SPI_CS1_MODE, 669 GPIO_SPI_CS1_MODE_MASK, 670 GPIO_SPI_CS1_MODE_MASK 671 }, 672 .regmap_size = 1, 673 }, 674 }; 675 676 /* shared */ 677 static const struct airoha_pinctrl_func_group pnand_func_group[] = { 678 { 679 .name = "pnand", 680 .regmap[0] = { 681 AIROHA_FUNC_MUX, 682 REG_GPIO_PON_MODE, 683 GPIO_PARALLEL_NAND_MODE_MASK, 684 GPIO_PARALLEL_NAND_MODE_MASK 685 }, 686 .regmap_size = 1, 687 }, 688 }; 689 690 static const struct airoha_pinctrl_func_group gpio_func_group[] = { 691 AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, 692 GPIO_PCIE_RESET0_MASK), 693 AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, 694 GPIO_PCIE_RESET1_MASK), 695 AIROHA_PINCTRL_GPIO_EXT("gpio30", GPIO30_FLASH_MODE_CFG, 696 I2C_SCL_GPIO_MODE_MASK), 697 AIROHA_PINCTRL_GPIO_EXT("gpio31", GPIO31_FLASH_MODE_CFG, 698 I2C_SDA_GPIO_MODE_MASK), 699 AIROHA_PINCTRL_GPIO("gpio32", SPI_CLK_GPIO_MODE_MASK), 700 AIROHA_PINCTRL_GPIO("gpio33", SPI_CS_GPIO_MODE_MASK), 701 AIROHA_PINCTRL_GPIO("gpio34", SPI_MOSI_GPIO_MODE_MASK), 702 AIROHA_PINCTRL_GPIO("gpio35", SPI_MISO_GPIO_MODE_MASK), 703 AIROHA_PINCTRL_GPIO_EXT("gpio36", GPIO36_FLASH_MODE_CFG, 704 UART_TXD_GPIO_MODE_MASK), 705 AIROHA_PINCTRL_GPIO_EXT("gpio37", GPIO37_FLASH_MODE_CFG, 706 UART_RXD_GPIO_MODE_MASK), 707 }; 708 709 /* 710 * On AN7563 a set GPIO_PCIE_RESET{0,1} bit routes the pad to its GPIO 711 * function, so the PCIe reset function must clear it. 712 */ 713 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { 714 { 715 .name = "pcie_reset0", 716 .regmap[0] = { 717 AIROHA_FUNC_MUX, 718 REG_GPIO_PON_MODE, 719 GPIO_PCIE_RESET0_MASK, 720 0 721 }, 722 .regmap_size = 1, 723 }, { 724 .name = "pcie_reset1", 725 .regmap[0] = { 726 AIROHA_FUNC_MUX, 727 REG_GPIO_PON_MODE, 728 GPIO_PCIE_RESET1_MASK, 729 0 730 }, 731 .regmap_size = 1, 732 }, 733 }; 734 735 static const struct airoha_pinctrl_func_group pwm_func_group[] = { 736 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), 737 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), 738 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), 739 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), 740 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), 741 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), 742 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), 743 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), 744 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), 745 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), 746 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), 747 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), 748 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), 749 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), 750 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), 751 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), 752 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), 753 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), 754 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), 755 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), 756 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), 757 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), 758 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), 759 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), 760 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), 761 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), 762 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), 763 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), 764 AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, 765 GPIO_PCIE_RESET0_MASK), 766 AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, 767 GPIO_PCIE_RESET1_MASK), 768 AIROHA_PINCTRL_PWM_EXT_SEC("gpio30", GPIO30_FLASH_MODE_CFG, 769 I2C_SCL_GPIO_MODE_MASK), 770 AIROHA_PINCTRL_PWM_EXT_SEC("gpio31", GPIO31_FLASH_MODE_CFG, 771 I2C_SDA_GPIO_MODE_MASK), 772 AIROHA_PINCTRL_PWM_EXT_SEC("gpio36", GPIO36_FLASH_MODE_CFG, 773 UART_TXD_GPIO_MODE_MASK), 774 AIROHA_PINCTRL_PWM_EXT_SEC("gpio37", GPIO37_FLASH_MODE_CFG, 775 UART_RXD_GPIO_MODE_MASK), 776 }; 777 778 /* 779 * LED pad mapping (datasheet table 4-9): 780 * GPIO8: LAN0_LED0, GPIO9: LAN1_LED0, GPIO10: LAN2_LED0, GPIO11: LAN3_LED0 781 * GPIO7: LAN0_LED1, GPIO6: LAN1_LED1, GPIO5: LAN2_LED1, GPIO4: LAN3_LED1 782 */ 783 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { 784 AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, 785 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 786 AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, 787 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 788 AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, 789 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 790 AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, 791 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 792 }; 793 794 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { 795 AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, 796 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 797 AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, 798 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 799 AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, 800 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 801 AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, 802 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 803 }; 804 805 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { 806 AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, 807 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 808 AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, 809 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 810 AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, 811 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 812 AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, 813 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 814 }; 815 816 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { 817 AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, 818 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 819 AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, 820 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 821 AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, 822 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 823 AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, 824 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 825 }; 826 827 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { 828 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 829 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 830 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 831 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 832 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 833 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 834 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 835 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 836 }; 837 838 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { 839 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 840 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 841 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 842 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 843 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 844 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 845 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 846 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 847 }; 848 849 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { 850 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 851 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 852 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 853 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 854 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 855 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 856 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 857 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 858 }; 859 860 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { 861 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 862 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 863 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 864 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 865 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 866 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 867 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 868 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 869 }; 870 871 static const struct airoha_pinctrl_func pinctrl_funcs[] = { 872 PINCTRL_FUNC_DESC("pon", pon), 873 PINCTRL_FUNC_DESC("sipo", sipo), 874 PINCTRL_FUNC_DESC("mdio", mdio), 875 PINCTRL_FUNC_DESC("uart", uart), 876 PINCTRL_FUNC_DESC("jtag", jtag), 877 PINCTRL_FUNC_DESC("pcm", pcm), 878 PINCTRL_FUNC_DESC("spi", spi), 879 PINCTRL_FUNC_DESC("pnand", pnand), 880 PINCTRL_FUNC_DESC("gpio", gpio), 881 PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), 882 PINCTRL_FUNC_DESC("pwm", pwm), 883 PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), 884 PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), 885 PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), 886 PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), 887 PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), 888 PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), 889 PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), 890 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), 891 }; 892 893 static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { 894 PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)), 895 PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)), 896 PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)), 897 PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)), 898 PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)), 899 PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)), 900 PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)), 901 PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)), 902 PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)), 903 PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)), 904 PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)), 905 PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)), 906 PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)), 907 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)), 908 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)), 909 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)), 910 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)), 911 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)), 912 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)), 913 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)), 914 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)), 915 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)), 916 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)), 917 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)), 918 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)), 919 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)), 920 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)), 921 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)), 922 PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 923 PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 924 PINCTRL_CONF_DESC(30, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 925 PINCTRL_CONF_DESC(31, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 926 PINCTRL_CONF_DESC(32, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 927 PINCTRL_CONF_DESC(33, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 928 PINCTRL_CONF_DESC(34, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 929 PINCTRL_CONF_DESC(35, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 930 PINCTRL_CONF_DESC(36, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 931 PINCTRL_CONF_DESC(37, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 932 }; 933 934 static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { 935 PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)), 936 PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)), 937 PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)), 938 PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)), 939 PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)), 940 PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)), 941 PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)), 942 PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)), 943 PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)), 944 PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)), 945 PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)), 946 PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)), 947 PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)), 948 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)), 949 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)), 950 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)), 951 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)), 952 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)), 953 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)), 954 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)), 955 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)), 956 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)), 957 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)), 958 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)), 959 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)), 960 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)), 961 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)), 962 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)), 963 PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 964 PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 965 PINCTRL_CONF_DESC(30, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 966 PINCTRL_CONF_DESC(31, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 967 PINCTRL_CONF_DESC(32, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 968 PINCTRL_CONF_DESC(33, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 969 PINCTRL_CONF_DESC(34, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 970 PINCTRL_CONF_DESC(35, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 971 PINCTRL_CONF_DESC(36, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 972 PINCTRL_CONF_DESC(37, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 973 }; 974 975 static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { 976 PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)), 977 PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)), 978 PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)), 979 PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)), 980 PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)), 981 PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)), 982 PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)), 983 PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)), 984 PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)), 985 PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)), 986 PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)), 987 PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)), 988 PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)), 989 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)), 990 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)), 991 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)), 992 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)), 993 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)), 994 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)), 995 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)), 996 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)), 997 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)), 998 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)), 999 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)), 1000 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)), 1001 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)), 1002 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)), 1003 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)), 1004 PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 1005 PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 1006 PINCTRL_CONF_DESC(30, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 1007 PINCTRL_CONF_DESC(31, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 1008 PINCTRL_CONF_DESC(32, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 1009 PINCTRL_CONF_DESC(33, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 1010 PINCTRL_CONF_DESC(34, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 1011 PINCTRL_CONF_DESC(35, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 1012 PINCTRL_CONF_DESC(36, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 1013 PINCTRL_CONF_DESC(37, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 1014 }; 1015 1016 static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { 1017 PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)), 1018 PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)), 1019 PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)), 1020 PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)), 1021 PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)), 1022 PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)), 1023 PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)), 1024 PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)), 1025 PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)), 1026 PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)), 1027 PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)), 1028 PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)), 1029 PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)), 1030 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)), 1031 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)), 1032 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)), 1033 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)), 1034 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)), 1035 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)), 1036 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)), 1037 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)), 1038 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)), 1039 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)), 1040 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)), 1041 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)), 1042 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)), 1043 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)), 1044 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)), 1045 PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 1046 PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 1047 PINCTRL_CONF_DESC(30, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 1048 PINCTRL_CONF_DESC(31, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 1049 PINCTRL_CONF_DESC(32, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 1050 PINCTRL_CONF_DESC(33, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 1051 PINCTRL_CONF_DESC(34, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 1052 PINCTRL_CONF_DESC(35, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 1053 PINCTRL_CONF_DESC(36, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 1054 PINCTRL_CONF_DESC(37, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 1055 }; 1056 1057 static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { 1058 PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), 1059 PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), 1060 }; 1061 1062 static const struct airoha_pinctrl_match_data pinctrl_match_data = { 1063 .chip_scu_compatible = "airoha,en7581-chip-scu", 1064 .pinctrl_name = KBUILD_MODNAME, 1065 .pinctrl_owner = THIS_MODULE, 1066 .pins = pinctrl_pins, 1067 .num_pins = ARRAY_SIZE(pinctrl_pins), 1068 .grps = pinctrl_groups, 1069 .num_grps = ARRAY_SIZE(pinctrl_groups), 1070 .funcs = pinctrl_funcs, 1071 .num_funcs = ARRAY_SIZE(pinctrl_funcs), 1072 .confs_info = { 1073 [AIROHA_PINCTRL_CONFS_PULLUP] = { 1074 .confs = pinctrl_pullup_conf, 1075 .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), 1076 }, 1077 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 1078 .confs = pinctrl_pulldown_conf, 1079 .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), 1080 }, 1081 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 1082 .confs = pinctrl_drive_e2_conf, 1083 .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), 1084 }, 1085 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 1086 .confs = pinctrl_drive_e4_conf, 1087 .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), 1088 }, 1089 [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { 1090 .confs = pinctrl_pcie_rst_od_conf, 1091 .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), 1092 }, 1093 }, 1094 }; 1095 1096 static const struct of_device_id airoha_pinctrl_of_match[] = { 1097 { .compatible = "airoha,an7563-pinctrl", .data = &pinctrl_match_data }, 1098 { /* sentinel */ } 1099 }; 1100 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); 1101 1102 static struct platform_driver airoha_pinctrl_driver = { 1103 .probe = airoha_pinctrl_probe, 1104 .driver = { 1105 .name = "pinctrl-airoha-an7563", 1106 .of_match_table = airoha_pinctrl_of_match, 1107 }, 1108 }; 1109 module_platform_driver(airoha_pinctrl_driver); 1110 1111 MODULE_LICENSE("GPL"); 1112 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 1113 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); 1114 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); 1115 MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7563 SoC"); 1116