1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> 5 * Author: Markus Gothe <markus.gothe@genexis.eu> 6 * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com> 7 * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> 8 */ 9 #include "airoha-common.h" 10 11 /* MUX */ 12 #define REG_GPIO_2ND_I2C_MODE 0x0210 13 #define GPIO_I2S_MODE_MASK BIT(12) 14 #define GPIO_I2C_SLAVE_MODE_MODE BIT(11) 15 #define GPIO_LAN3_LED1_MODE_MASK BIT(10) 16 #define GPIO_LAN3_LED0_MODE_MASK BIT(9) 17 #define GPIO_LAN2_LED1_MODE_MASK BIT(8) 18 #define GPIO_LAN2_LED0_MODE_MASK BIT(7) 19 #define GPIO_LAN1_LED1_MODE_MASK BIT(6) 20 #define GPIO_LAN1_LED0_MODE_MASK BIT(5) 21 #define GPIO_LAN0_LED1_MODE_MASK BIT(4) 22 #define GPIO_LAN0_LED0_MODE_MASK BIT(3) 23 #define PON_TOD_1PPS_MODE_MASK BIT(2) 24 #define GSW_TOD_1PPS_MODE_MASK BIT(1) 25 #define GPIO_2ND_I2C_MODE_MASK BIT(0) 26 27 #define REG_GPIO_SPI_CS1_MODE 0x0214 28 #define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) 29 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) 30 #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) 31 #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) 32 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) 33 #define GPIO_PCM_SPI_MODE_MASK BIT(16) 34 #define GPIO_PCM2_MODE_MASK BIT(13) 35 #define GPIO_PCM1_MODE_MASK BIT(12) 36 #define GPIO_PCM_INT_MODE_MASK BIT(9) 37 #define GPIO_PCM_RESET_MODE_MASK BIT(8) 38 #define GPIO_SPI_QUAD_MODE_MASK BIT(4) 39 #define GPIO_SPI_CS1_MODE_MASK BIT(0) 40 41 #define REG_GPIO_PON_MODE 0x0218 42 #define GPIO_SGMII_MDIO_MODE_MASK BIT(13) 43 #define SIPO_RCLK_MODE_MASK BIT(11) 44 #define GPIO_PCIE_RESET1_MASK BIT(10) 45 #define GPIO_PCIE_RESET0_MASK BIT(9) 46 #define GPIO_UART2_MODE_MASK BIT(3) 47 #define GPIO_SIPO_MODE_MASK BIT(2) 48 #define GPIO_PON_MODE_MASK BIT(0) 49 50 #define REG_NPU_UART_EN 0x0220 51 #define JTAG_UDI_EN_MASK BIT(4) 52 #define JTAG_DFD_EN_MASK BIT(3) 53 #define NPU_UART_EN_MASK BIT(2) 54 55 #define REG_FORCE_GPIO_EN 0x0224 56 #define FORCE_GPIO_EN(n) BIT(n) 57 58 /* LED MAP */ 59 #define REG_LAN_LED0_MAPPING 0x0278 60 #define REG_LAN_LED1_MAPPING 0x027c 61 62 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12) 63 #define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) 64 65 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8) 66 #define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) 67 68 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4) 69 #define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) 70 71 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0) 72 #define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) 73 74 /* CONF */ 75 #define REG_I2C_SDA_E2 0x001c 76 #define SPI_MISO_E2_MASK BIT(13) 77 #define SPI_MOSI_E2_MASK BIT(12) 78 #define SPI_CLK_E2_MASK BIT(11) 79 #define SPI_CS0_E2_MASK BIT(10) 80 #define PCIE1_RESET_E2_MASK BIT(9) 81 #define PCIE0_RESET_E2_MASK BIT(8) 82 #define UART1_RXD_E2_MASK BIT(3) 83 #define UART1_TXD_E2_MASK BIT(2) 84 #define I2C_SCL_E2_MASK BIT(1) 85 #define I2C_SDA_E2_MASK BIT(0) 86 87 #define REG_I2C_SDA_E4 0x0020 88 #define SPI_MISO_E4_MASK BIT(13) 89 #define SPI_MOSI_E4_MASK BIT(12) 90 #define SPI_CLK_E4_MASK BIT(11) 91 #define SPI_CS0_E4_MASK BIT(10) 92 #define PCIE1_RESET_E4_MASK BIT(9) 93 #define PCIE0_RESET_E4_MASK BIT(8) 94 #define UART1_RXD_E4_MASK BIT(3) 95 #define UART1_TXD_E4_MASK BIT(2) 96 #define I2C_SCL_E4_MASK BIT(1) 97 #define I2C_SDA_E4_MASK BIT(0) 98 99 #define REG_GPIO_L_E2 0x0024 100 #define REG_GPIO_L_E4 0x0028 101 102 #define REG_I2C_SDA_PU 0x0044 103 #define SPI_MISO_PU_MASK BIT(13) 104 #define SPI_MOSI_PU_MASK BIT(12) 105 #define SPI_CLK_PU_MASK BIT(11) 106 #define SPI_CS0_PU_MASK BIT(10) 107 #define PCIE1_RESET_PU_MASK BIT(9) 108 #define PCIE0_RESET_PU_MASK BIT(8) 109 #define UART1_RXD_PU_MASK BIT(3) 110 #define UART1_TXD_PU_MASK BIT(2) 111 #define I2C_SCL_PU_MASK BIT(1) 112 #define I2C_SDA_PU_MASK BIT(0) 113 114 #define REG_I2C_SDA_PD 0x0048 115 #define SPI_MISO_PD_MASK BIT(13) 116 #define SPI_MOSI_PD_MASK BIT(12) 117 #define SPI_CLK_PD_MASK BIT(11) 118 #define SPI_CS0_PD_MASK BIT(10) 119 #define PCIE1_RESET_PD_MASK BIT(9) 120 #define PCIE0_RESET_PD_MASK BIT(8) 121 #define UART1_RXD_PD_MASK BIT(3) 122 #define UART1_TXD_PD_MASK BIT(2) 123 #define I2C_SCL_PD_MASK BIT(1) 124 #define I2C_SDA_PD_MASK BIT(0) 125 126 #define REG_GPIO_L_PU 0x004c 127 #define REG_GPIO_L_PD 0x0050 128 129 /* PWM MODE CONF */ 130 #define REG_GPIO_FLASH_MODE_CFG 0x0034 131 #define GPIO15_FLASH_MODE_CFG BIT(15) 132 #define GPIO14_FLASH_MODE_CFG BIT(14) 133 #define GPIO13_FLASH_MODE_CFG BIT(13) 134 #define GPIO12_FLASH_MODE_CFG BIT(12) 135 #define GPIO11_FLASH_MODE_CFG BIT(11) 136 #define GPIO10_FLASH_MODE_CFG BIT(10) 137 #define GPIO9_FLASH_MODE_CFG BIT(9) 138 #define GPIO8_FLASH_MODE_CFG BIT(8) 139 #define GPIO7_FLASH_MODE_CFG BIT(7) 140 #define GPIO6_FLASH_MODE_CFG BIT(6) 141 #define GPIO5_FLASH_MODE_CFG BIT(5) 142 #define GPIO4_FLASH_MODE_CFG BIT(4) 143 #define GPIO3_FLASH_MODE_CFG BIT(3) 144 #define GPIO2_FLASH_MODE_CFG BIT(2) 145 #define GPIO1_FLASH_MODE_CFG BIT(1) 146 #define GPIO0_FLASH_MODE_CFG BIT(0) 147 148 /* PWM MODE CONF EXT */ 149 #define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 150 #define GPIO51_FLASH_MODE_CFG BIT(31) 151 #define GPIO50_FLASH_MODE_CFG BIT(30) 152 #define GPIO49_FLASH_MODE_CFG BIT(29) 153 #define GPIO48_FLASH_MODE_CFG BIT(28) 154 #define GPIO47_FLASH_MODE_CFG BIT(27) 155 #define GPIO46_FLASH_MODE_CFG BIT(26) 156 #define GPIO45_FLASH_MODE_CFG BIT(25) 157 #define GPIO44_FLASH_MODE_CFG BIT(24) 158 #define GPIO43_FLASH_MODE_CFG BIT(23) 159 #define GPIO42_FLASH_MODE_CFG BIT(22) 160 #define GPIO41_FLASH_MODE_CFG BIT(21) 161 #define GPIO40_FLASH_MODE_CFG BIT(20) 162 #define GPIO39_FLASH_MODE_CFG BIT(19) 163 #define GPIO38_FLASH_MODE_CFG BIT(18) 164 #define GPIO37_FLASH_MODE_CFG BIT(17) 165 #define GPIO36_FLASH_MODE_CFG BIT(16) 166 #define GPIO31_FLASH_MODE_CFG BIT(15) 167 #define GPIO30_FLASH_MODE_CFG BIT(14) 168 #define GPIO29_FLASH_MODE_CFG BIT(13) 169 #define GPIO28_FLASH_MODE_CFG BIT(12) 170 #define GPIO27_FLASH_MODE_CFG BIT(11) 171 #define GPIO26_FLASH_MODE_CFG BIT(10) 172 #define GPIO25_FLASH_MODE_CFG BIT(9) 173 #define GPIO24_FLASH_MODE_CFG BIT(8) 174 #define GPIO23_FLASH_MODE_CFG BIT(7) 175 #define GPIO22_FLASH_MODE_CFG BIT(6) 176 #define GPIO21_FLASH_MODE_CFG BIT(5) 177 #define GPIO20_FLASH_MODE_CFG BIT(4) 178 #define GPIO19_FLASH_MODE_CFG BIT(3) 179 #define GPIO18_FLASH_MODE_CFG BIT(2) 180 #define GPIO17_FLASH_MODE_CFG BIT(1) 181 #define GPIO16_FLASH_MODE_CFG BIT(0) 182 183 #define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ 184 { \ 185 .name = (gpio), \ 186 .regmap[0] = { \ 187 AIROHA_FUNC_MUX, \ 188 REG_GPIO_PON_MODE, \ 189 (mux_val), \ 190 (mux_val) \ 191 }, \ 192 .regmap_size = 1, \ 193 } 194 195 #define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ 196 { \ 197 .name = (gpio), \ 198 .regmap[0] = { \ 199 AIROHA_FUNC_PWM_EXT_MUX, \ 200 REG_GPIO_FLASH_MODE_CFG_EXT, \ 201 (mux_val), \ 202 0 \ 203 }, \ 204 .regmap[1] = { \ 205 AIROHA_FUNC_MUX, \ 206 REG_GPIO_PON_MODE, \ 207 (smux_val), \ 208 (smux_val) \ 209 }, \ 210 .regmap_size = 2, \ 211 } 212 213 /* PWM */ 214 #define AIROHA_PINCTRL_PWM(gpio, mux_val) \ 215 { \ 216 .name = (gpio), \ 217 .regmap[0] = { \ 218 AIROHA_FUNC_PWM_MUX, \ 219 REG_GPIO_FLASH_MODE_CFG, \ 220 (mux_val), \ 221 (mux_val) \ 222 }, \ 223 .regmap_size = 1, \ 224 } 225 226 #define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ 227 { \ 228 .name = (gpio), \ 229 .regmap[0] = { \ 230 AIROHA_FUNC_PWM_EXT_MUX, \ 231 REG_GPIO_FLASH_MODE_CFG_EXT, \ 232 (mux_val), \ 233 (mux_val) \ 234 }, \ 235 .regmap_size = 1, \ 236 } 237 238 #define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ 239 { \ 240 .name = (gpio), \ 241 .regmap[0] = { \ 242 AIROHA_FUNC_PWM_EXT_MUX, \ 243 REG_GPIO_FLASH_MODE_CFG_EXT, \ 244 (mux_val), \ 245 (mux_val) \ 246 }, \ 247 .regmap[1] = { \ 248 AIROHA_FUNC_MUX, \ 249 REG_GPIO_PON_MODE, \ 250 (smux_val), \ 251 (smux_val) \ 252 }, \ 253 .regmap_size = 2, \ 254 } 255 256 #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ 257 { \ 258 .name = (gpio), \ 259 .regmap[0] = { \ 260 AIROHA_FUNC_MUX, \ 261 REG_GPIO_2ND_I2C_MODE, \ 262 (mux_val), \ 263 (mux_val), \ 264 }, \ 265 .regmap[1] = { \ 266 AIROHA_FUNC_MUX, \ 267 REG_LAN_LED0_MAPPING, \ 268 (map_mask), \ 269 (map_val), \ 270 }, \ 271 .regmap_size = 2, \ 272 } 273 274 #define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ 275 { \ 276 .name = (gpio), \ 277 .regmap[0] = { \ 278 AIROHA_FUNC_MUX, \ 279 REG_GPIO_2ND_I2C_MODE, \ 280 (mux_val), \ 281 (mux_val), \ 282 }, \ 283 .regmap[1] = { \ 284 AIROHA_FUNC_MUX, \ 285 REG_LAN_LED1_MAPPING, \ 286 (map_mask), \ 287 (map_val), \ 288 }, \ 289 .regmap_size = 2, \ 290 } 291 292 static struct pinctrl_pin_desc pinctrl_pins[] = { 293 PINCTRL_PIN(2, "i2c_sda"), 294 PINCTRL_PIN(3, "i2c_scl"), 295 PINCTRL_PIN(4, "spi_cs0"), 296 PINCTRL_PIN(5, "spi_clk"), 297 PINCTRL_PIN(6, "spi_mosi"), 298 PINCTRL_PIN(7, "spi_miso"), 299 PINCTRL_PIN(8, "uart1_txd"), 300 PINCTRL_PIN(9, "uart1_rxd"), 301 PINCTRL_PIN(12, "gpio0"), 302 PINCTRL_PIN(13, "gpio1"), 303 PINCTRL_PIN(14, "gpio2"), 304 PINCTRL_PIN(15, "gpio3"), 305 PINCTRL_PIN(16, "gpio4"), 306 PINCTRL_PIN(17, "gpio5"), 307 PINCTRL_PIN(18, "gpio6"), 308 PINCTRL_PIN(19, "gpio7"), 309 PINCTRL_PIN(20, "gpio8"), 310 PINCTRL_PIN(21, "gpio9"), 311 PINCTRL_PIN(22, "gpio10"), 312 PINCTRL_PIN(23, "gpio11"), 313 PINCTRL_PIN(24, "gpio12"), 314 PINCTRL_PIN(25, "gpio13"), 315 PINCTRL_PIN(26, "gpio14"), 316 PINCTRL_PIN(27, "gpio15"), 317 PINCTRL_PIN(28, "gpio16"), 318 PINCTRL_PIN(29, "gpio17"), 319 PINCTRL_PIN(30, "gpio18"), 320 PINCTRL_PIN(31, "gpio19"), 321 PINCTRL_PIN(32, "gpio20"), 322 PINCTRL_PIN(33, "gpio21"), 323 PINCTRL_PIN(34, "gpio22"), 324 PINCTRL_PIN(35, "gpio23"), 325 PINCTRL_PIN(36, "gpio24"), 326 PINCTRL_PIN(37, "gpio25"), 327 PINCTRL_PIN(38, "gpio26"), 328 PINCTRL_PIN(39, "gpio27"), 329 PINCTRL_PIN(40, "pcie_reset0"), 330 PINCTRL_PIN(41, "pcie_reset1"), 331 }; 332 333 static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 }; 334 static const int pon_tod_1pps_pins[] = { 21 }; 335 static const int gsw_tod_1pps_pins[] = { 21 }; 336 static const int sipo_pins[] = { 13, 38 }; 337 static const int sipo_rclk_pins[] = { 13, 30, 38 }; 338 static const int mdio_pins[] = { 20, 21 }; 339 static const int uart2_pins[] = { 20, 21 }; 340 static const int npu_uart_pins[] = { 13, 38 }; 341 static const int i2c0_pins[] = { 2, 3 }; 342 static const int i2c1_pins[] = { 14, 15 }; 343 static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 }; 344 static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 }; 345 static const int i2s_pins[] = { 16, 17, 18, 19 }; 346 static const int pcm1_pins[] = { 24, 25, 26, 27 }; 347 static const int pcm2_pins[] = { 16, 17, 18, 19 }; 348 static const int spi_pins[] = { 4, 5, 6, 7 }; 349 static const int spi_quad_pins[] = { 14, 15 }; 350 static const int spi_cs1_pins[] = { 21 }; 351 static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 }; 352 static const int pcm_spi_int_pins[] = { 15 }; 353 static const int pcm_spi_rst_pins[] = { 14 }; 354 static const int pcm_spi_cs1_pins[] = { 22 }; 355 static const int pcm_spi_cs2_p128_pins[] = { 39 }; 356 static const int pcm_spi_cs2_p156_pins[] = { 39 }; 357 static const int pcm_spi_cs3_pins[] = { 20 }; 358 static const int pcm_spi_cs4_pins[] = { 23 }; 359 static const int gpio0_pins[] = { 12 }; 360 static const int gpio1_pins[] = { 13 }; 361 static const int gpio2_pins[] = { 14 }; 362 static const int gpio3_pins[] = { 15 }; 363 static const int gpio4_pins[] = { 16 }; 364 static const int gpio5_pins[] = { 17 }; 365 static const int gpio6_pins[] = { 18 }; 366 static const int gpio7_pins[] = { 19 }; 367 static const int gpio8_pins[] = { 20 }; 368 static const int gpio9_pins[] = { 21 }; 369 static const int gpio10_pins[] = { 22 }; 370 static const int gpio11_pins[] = { 23 }; 371 static const int gpio12_pins[] = { 24 }; 372 static const int gpio13_pins[] = { 25 }; 373 static const int gpio14_pins[] = { 26 }; 374 static const int gpio15_pins[] = { 27 }; 375 static const int gpio16_pins[] = { 28 }; 376 static const int gpio17_pins[] = { 29 }; 377 static const int gpio18_pins[] = { 30 }; 378 static const int gpio19_pins[] = { 31 }; 379 static const int gpio20_pins[] = { 32 }; 380 static const int gpio21_pins[] = { 33 }; 381 static const int gpio22_pins[] = { 34 }; 382 static const int gpio23_pins[] = { 35 }; 383 static const int gpio24_pins[] = { 36 }; 384 static const int gpio25_pins[] = { 37 }; 385 static const int gpio26_pins[] = { 38 }; 386 static const int gpio27_pins[] = { 39 }; 387 static const int gpio28_pins[] = { 40 }; 388 static const int gpio29_pins[] = { 41 }; 389 static const int pcie_reset0_pins[] = { 40 }; 390 static const int pcie_reset1_pins[] = { 41 }; 391 392 static const struct pingroup pinctrl_groups[] = { 393 PINCTRL_PIN_GROUP("pon", pon), 394 PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), 395 PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), 396 PINCTRL_PIN_GROUP("sipo", sipo), 397 PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), 398 PINCTRL_PIN_GROUP("mdio", mdio), 399 PINCTRL_PIN_GROUP("uart2", uart2), 400 PINCTRL_PIN_GROUP("npu_uart", npu_uart), 401 PINCTRL_PIN_GROUP("i2c0", i2c0), 402 PINCTRL_PIN_GROUP("i2c1", i2c1), 403 PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), 404 PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), 405 PINCTRL_PIN_GROUP("i2s", i2s), 406 PINCTRL_PIN_GROUP("pcm1", pcm1), 407 PINCTRL_PIN_GROUP("pcm2", pcm2), 408 PINCTRL_PIN_GROUP("spi", spi), 409 PINCTRL_PIN_GROUP("spi_quad", spi_quad), 410 PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), 411 PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), 412 PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), 413 PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), 414 PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), 415 PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), 416 PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), 417 PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), 418 PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), 419 PINCTRL_PIN_GROUP("gpio0", gpio0), 420 PINCTRL_PIN_GROUP("gpio1", gpio1), 421 PINCTRL_PIN_GROUP("gpio2", gpio2), 422 PINCTRL_PIN_GROUP("gpio3", gpio3), 423 PINCTRL_PIN_GROUP("gpio4", gpio4), 424 PINCTRL_PIN_GROUP("gpio5", gpio5), 425 PINCTRL_PIN_GROUP("gpio6", gpio6), 426 PINCTRL_PIN_GROUP("gpio7", gpio7), 427 PINCTRL_PIN_GROUP("gpio8", gpio8), 428 PINCTRL_PIN_GROUP("gpio9", gpio9), 429 PINCTRL_PIN_GROUP("gpio10", gpio10), 430 PINCTRL_PIN_GROUP("gpio11", gpio11), 431 PINCTRL_PIN_GROUP("gpio12", gpio12), 432 PINCTRL_PIN_GROUP("gpio13", gpio13), 433 PINCTRL_PIN_GROUP("gpio14", gpio14), 434 PINCTRL_PIN_GROUP("gpio15", gpio15), 435 PINCTRL_PIN_GROUP("gpio16", gpio16), 436 PINCTRL_PIN_GROUP("gpio17", gpio17), 437 PINCTRL_PIN_GROUP("gpio18", gpio18), 438 PINCTRL_PIN_GROUP("gpio19", gpio19), 439 PINCTRL_PIN_GROUP("gpio20", gpio20), 440 PINCTRL_PIN_GROUP("gpio21", gpio21), 441 PINCTRL_PIN_GROUP("gpio22", gpio22), 442 PINCTRL_PIN_GROUP("gpio23", gpio23), 443 PINCTRL_PIN_GROUP("gpio24", gpio24), 444 PINCTRL_PIN_GROUP("gpio25", gpio25), 445 PINCTRL_PIN_GROUP("gpio26", gpio26), 446 PINCTRL_PIN_GROUP("gpio27", gpio27), 447 PINCTRL_PIN_GROUP("gpio28", gpio28), 448 PINCTRL_PIN_GROUP("gpio29", gpio29), 449 PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), 450 PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), 451 }; 452 453 static const char *const pon_groups[] = { "pon" }; 454 static const char *const tod_1pps_groups[] = { 455 "pon_tod_1pps", "gsw_tod_1pps" 456 }; 457 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; 458 static const char *const mdio_groups[] = { "mdio" }; 459 static const char *const uart_groups[] = { "uart2", "npu_uart" }; 460 static const char *const i2c_groups[] = { "i2c1" }; 461 static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; 462 static const char *const pcm_groups[] = { "pcm1", "pcm2" }; 463 static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; 464 static const char *const pcm_spi_groups[] = { 465 "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", 466 "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" 467 }; 468 static const char *const i2s_groups[] = { "i2s" }; 469 static const char *const gpio_groups[] = { "gpio28", "gpio29" }; 470 static const char *const pcie_reset_groups[] = { 471 "pcie_reset0", "pcie_reset1" 472 }; 473 static const char *const pwm_groups[] = { 474 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 475 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 476 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 477 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 478 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29" 479 }; 480 static const char *const phy1_led0_groups[] = { 481 "gpio22", "gpio23", "gpio24", "gpio25" 482 }; 483 static const char *const phy2_led0_groups[] = { 484 "gpio22", "gpio23", "gpio24", "gpio25" 485 }; 486 static const char *const phy3_led0_groups[] = { 487 "gpio22", "gpio23", "gpio24", "gpio25" 488 }; 489 static const char *const phy4_led0_groups[] = { 490 "gpio22", "gpio23", "gpio24", "gpio25" 491 }; 492 static const char *const phy1_led1_groups[] = { 493 "gpio7", "gpio6", "gpio5", "gpio4" 494 }; 495 static const char *const phy2_led1_groups[] = { 496 "gpio7", "gpio6", "gpio5", "gpio4" 497 }; 498 static const char *const phy3_led1_groups[] = { 499 "gpio7", "gpio6", "gpio5", "gpio4" 500 }; 501 static const char *const phy4_led1_groups[] = { 502 "gpio7", "gpio6", "gpio5", "gpio4" 503 }; 504 505 static const struct airoha_pinctrl_func_group pon_func_group[] = { 506 { 507 .name = "pon", 508 .regmap[0] = { 509 AIROHA_FUNC_MUX, 510 REG_GPIO_PON_MODE, 511 GPIO_PON_MODE_MASK, 512 GPIO_PON_MODE_MASK 513 }, 514 .regmap_size = 1, 515 }, 516 }; 517 518 static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { 519 { 520 .name = "pon_tod_1pps", 521 .regmap[0] = { 522 AIROHA_FUNC_MUX, 523 REG_GPIO_2ND_I2C_MODE, 524 PON_TOD_1PPS_MODE_MASK, 525 PON_TOD_1PPS_MODE_MASK 526 }, 527 .regmap_size = 1, 528 }, { 529 .name = "gsw_tod_1pps", 530 .regmap[0] = { 531 AIROHA_FUNC_MUX, 532 REG_GPIO_2ND_I2C_MODE, 533 GSW_TOD_1PPS_MODE_MASK, 534 GSW_TOD_1PPS_MODE_MASK 535 }, 536 .regmap_size = 1, 537 }, 538 }; 539 540 static const struct airoha_pinctrl_func_group sipo_func_group[] = { 541 { 542 .name = "sipo", 543 .regmap[0] = { 544 AIROHA_FUNC_MUX, 545 REG_GPIO_PON_MODE, 546 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 547 GPIO_SIPO_MODE_MASK 548 }, 549 .regmap_size = 1, 550 }, { 551 .name = "sipo_rclk", 552 .regmap[0] = { 553 AIROHA_FUNC_MUX, 554 REG_GPIO_PON_MODE, 555 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 556 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK 557 }, 558 .regmap_size = 1, 559 }, 560 }; 561 562 static const struct airoha_pinctrl_func_group mdio_func_group[] = { 563 { 564 .name = "mdio", 565 .regmap[0] = { 566 AIROHA_FUNC_MUX, 567 REG_GPIO_PON_MODE, 568 GPIO_SGMII_MDIO_MODE_MASK, 569 GPIO_SGMII_MDIO_MODE_MASK 570 }, 571 .regmap_size = 1, 572 }, 573 }; 574 575 static const struct airoha_pinctrl_func_group uart_func_group[] = { 576 { 577 .name = "uart2", 578 .regmap[0] = { 579 AIROHA_FUNC_MUX, 580 REG_GPIO_PON_MODE, 581 GPIO_UART2_MODE_MASK, 582 GPIO_UART2_MODE_MASK 583 }, 584 .regmap_size = 1, 585 }, { 586 .name = "npu_uart", 587 .regmap[0] = { 588 AIROHA_FUNC_MUX, 589 REG_NPU_UART_EN, 590 NPU_UART_EN_MASK, 591 NPU_UART_EN_MASK 592 }, 593 .regmap_size = 1, 594 } 595 }; 596 597 static const struct airoha_pinctrl_func_group i2c_func_group[] = { 598 { 599 .name = "i2c1", 600 .regmap[0] = { 601 AIROHA_FUNC_MUX, 602 REG_GPIO_2ND_I2C_MODE, 603 GPIO_2ND_I2C_MODE_MASK, 604 GPIO_2ND_I2C_MODE_MASK 605 }, 606 .regmap_size = 1, 607 }, 608 }; 609 610 static const struct airoha_pinctrl_func_group jtag_func_group[] = { 611 { 612 .name = "jtag_udi", 613 .regmap[0] = { 614 AIROHA_FUNC_MUX, 615 REG_NPU_UART_EN, 616 JTAG_UDI_EN_MASK, 617 JTAG_UDI_EN_MASK 618 }, 619 .regmap_size = 1, 620 }, { 621 .name = "jtag_dfd", 622 .regmap[0] = { 623 AIROHA_FUNC_MUX, 624 REG_NPU_UART_EN, 625 JTAG_DFD_EN_MASK, 626 JTAG_DFD_EN_MASK 627 }, 628 .regmap_size = 1, 629 }, 630 }; 631 632 static const struct airoha_pinctrl_func_group pcm_func_group[] = { 633 { 634 .name = "pcm1", 635 .regmap[0] = { 636 AIROHA_FUNC_MUX, 637 REG_GPIO_SPI_CS1_MODE, 638 GPIO_PCM1_MODE_MASK, 639 GPIO_PCM1_MODE_MASK 640 }, 641 .regmap_size = 1, 642 }, { 643 .name = "pcm2", 644 .regmap[0] = { 645 AIROHA_FUNC_MUX, 646 REG_GPIO_SPI_CS1_MODE, 647 GPIO_PCM2_MODE_MASK, 648 GPIO_PCM2_MODE_MASK 649 }, 650 .regmap_size = 1, 651 }, 652 }; 653 654 static const struct airoha_pinctrl_func_group spi_func_group[] = { 655 { 656 .name = "spi_quad", 657 .regmap[0] = { 658 AIROHA_FUNC_MUX, 659 REG_GPIO_SPI_CS1_MODE, 660 GPIO_SPI_QUAD_MODE_MASK, 661 GPIO_SPI_QUAD_MODE_MASK 662 }, 663 .regmap_size = 1, 664 }, { 665 .name = "spi_cs1", 666 .regmap[0] = { 667 AIROHA_FUNC_MUX, 668 REG_GPIO_SPI_CS1_MODE, 669 GPIO_SPI_CS1_MODE_MASK, 670 GPIO_SPI_CS1_MODE_MASK 671 }, 672 .regmap_size = 1, 673 }, 674 }; 675 676 static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { 677 { 678 .name = "pcm_spi", 679 .regmap[0] = { 680 AIROHA_FUNC_MUX, 681 REG_GPIO_SPI_CS1_MODE, 682 GPIO_PCM_SPI_MODE_MASK, 683 GPIO_PCM_SPI_MODE_MASK 684 }, 685 .regmap_size = 1, 686 }, { 687 .name = "pcm_spi_int", 688 .regmap[0] = { 689 AIROHA_FUNC_MUX, 690 REG_GPIO_SPI_CS1_MODE, 691 GPIO_PCM_INT_MODE_MASK, 692 GPIO_PCM_INT_MODE_MASK 693 }, 694 .regmap_size = 1, 695 }, { 696 .name = "pcm_spi_rst", 697 .regmap[0] = { 698 AIROHA_FUNC_MUX, 699 REG_GPIO_SPI_CS1_MODE, 700 GPIO_PCM_RESET_MODE_MASK, 701 GPIO_PCM_RESET_MODE_MASK 702 }, 703 .regmap_size = 1, 704 }, { 705 .name = "pcm_spi_cs1", 706 .regmap[0] = { 707 AIROHA_FUNC_MUX, 708 REG_GPIO_SPI_CS1_MODE, 709 GPIO_PCM_SPI_CS1_MODE_MASK, 710 GPIO_PCM_SPI_CS1_MODE_MASK 711 }, 712 .regmap_size = 1, 713 }, { 714 .name = "pcm_spi_cs2_p128", 715 .regmap[0] = { 716 AIROHA_FUNC_MUX, 717 REG_GPIO_SPI_CS1_MODE, 718 GPIO_PCM_SPI_CS2_MODE_P128_MASK, 719 GPIO_PCM_SPI_CS2_MODE_P128_MASK 720 }, 721 .regmap_size = 1, 722 }, { 723 .name = "pcm_spi_cs2_p156", 724 .regmap[0] = { 725 AIROHA_FUNC_MUX, 726 REG_GPIO_SPI_CS1_MODE, 727 GPIO_PCM_SPI_CS2_MODE_P156_MASK, 728 GPIO_PCM_SPI_CS2_MODE_P156_MASK 729 }, 730 .regmap_size = 1, 731 }, { 732 .name = "pcm_spi_cs3", 733 .regmap[0] = { 734 AIROHA_FUNC_MUX, 735 REG_GPIO_SPI_CS1_MODE, 736 GPIO_PCM_SPI_CS3_MODE_MASK, 737 GPIO_PCM_SPI_CS3_MODE_MASK 738 }, 739 .regmap_size = 1, 740 }, { 741 .name = "pcm_spi_cs4", 742 .regmap[0] = { 743 AIROHA_FUNC_MUX, 744 REG_GPIO_SPI_CS1_MODE, 745 GPIO_PCM_SPI_CS4_MODE_MASK, 746 GPIO_PCM_SPI_CS4_MODE_MASK 747 }, 748 .regmap_size = 1, 749 }, 750 }; 751 752 static const struct airoha_pinctrl_func_group i2s_func_group[] = { 753 { 754 .name = "i2s", 755 .regmap[0] = { 756 AIROHA_FUNC_MUX, 757 REG_GPIO_2ND_I2C_MODE, 758 GPIO_I2S_MODE_MASK, 759 GPIO_I2S_MODE_MASK 760 }, 761 .regmap_size = 1, 762 }, 763 }; 764 765 static const struct airoha_pinctrl_func_group gpio_func_group[] = { 766 AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, 767 GPIO_PCIE_RESET0_MASK), 768 AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, 769 GPIO_PCIE_RESET1_MASK), 770 }; 771 772 static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { 773 { 774 .name = "pcie_reset0", 775 .regmap[0] = { 776 AIROHA_FUNC_MUX, 777 REG_GPIO_PON_MODE, 778 GPIO_PCIE_RESET0_MASK, 779 0 780 }, 781 .regmap_size = 1, 782 }, { 783 .name = "pcie_reset1", 784 .regmap[0] = { 785 AIROHA_FUNC_MUX, 786 REG_GPIO_PON_MODE, 787 GPIO_PCIE_RESET1_MASK, 788 0 789 }, 790 .regmap_size = 1, 791 }, 792 }; 793 794 static const struct airoha_pinctrl_func_group pwm_func_group[] = { 795 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), 796 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), 797 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), 798 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), 799 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), 800 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), 801 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), 802 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), 803 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), 804 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), 805 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), 806 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), 807 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), 808 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), 809 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), 810 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), 811 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), 812 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), 813 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), 814 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), 815 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), 816 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), 817 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), 818 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), 819 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), 820 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), 821 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), 822 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), 823 AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, 824 GPIO_PCIE_RESET0_MASK), 825 AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, 826 GPIO_PCIE_RESET1_MASK), 827 }; 828 829 static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { 830 AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, 831 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 832 AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, 833 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 834 AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, 835 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 836 AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, 837 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 838 }; 839 840 static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { 841 AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, 842 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 843 AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, 844 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 845 AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, 846 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 847 AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, 848 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 849 }; 850 851 static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { 852 AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, 853 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 854 AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, 855 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 856 AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, 857 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 858 AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, 859 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 860 }; 861 862 static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { 863 AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, 864 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 865 AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, 866 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 867 AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, 868 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 869 AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, 870 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 871 }; 872 873 static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { 874 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 875 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 876 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 877 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 878 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 879 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 880 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 881 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 882 }; 883 884 static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { 885 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 886 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 887 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 888 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 889 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 890 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 891 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 892 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 893 }; 894 895 static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { 896 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 897 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 898 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 899 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 900 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 901 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 902 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 903 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 904 }; 905 906 static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { 907 AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, 908 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 909 AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, 910 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 911 AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, 912 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 913 AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, 914 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 915 }; 916 917 static const struct airoha_pinctrl_func pinctrl_funcs[] = { 918 PINCTRL_FUNC_DESC("pon", pon), 919 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), 920 PINCTRL_FUNC_DESC("sipo", sipo), 921 PINCTRL_FUNC_DESC("mdio", mdio), 922 PINCTRL_FUNC_DESC("uart", uart), 923 PINCTRL_FUNC_DESC("i2c", i2c), 924 PINCTRL_FUNC_DESC("jtag", jtag), 925 PINCTRL_FUNC_DESC("pcm", pcm), 926 PINCTRL_FUNC_DESC("spi", spi), 927 PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), 928 PINCTRL_FUNC_DESC("i2s", i2s), 929 PINCTRL_FUNC_DESC("gpio", gpio), 930 PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), 931 PINCTRL_FUNC_DESC("pwm", pwm), 932 PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), 933 PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), 934 PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), 935 PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), 936 PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), 937 PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), 938 PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), 939 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), 940 }; 941 942 static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { 943 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 944 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 945 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 946 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 947 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 948 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 949 PINCTRL_CONF_DESC(8, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 950 PINCTRL_CONF_DESC(9, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 951 PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), 952 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), 953 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), 954 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), 955 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), 956 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), 957 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), 958 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), 959 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), 960 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), 961 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), 962 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), 963 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), 964 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), 965 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), 966 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), 967 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), 968 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), 969 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), 970 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)), 971 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), 972 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), 973 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), 974 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), 975 PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), 976 PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), 977 PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), 978 PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), 979 PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 980 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 981 }; 982 983 static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { 984 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 985 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 986 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 987 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 988 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 989 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 990 PINCTRL_CONF_DESC(8, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 991 PINCTRL_CONF_DESC(9, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 992 PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), 993 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), 994 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), 995 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), 996 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), 997 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), 998 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), 999 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), 1000 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), 1001 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), 1002 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), 1003 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), 1004 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), 1005 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), 1006 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), 1007 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), 1008 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), 1009 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), 1010 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), 1011 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)), 1012 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), 1013 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), 1014 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), 1015 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), 1016 PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), 1017 PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), 1018 PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), 1019 PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), 1020 PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 1021 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 1022 }; 1023 1024 static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { 1025 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 1026 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 1027 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 1028 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 1029 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 1030 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 1031 PINCTRL_CONF_DESC(8, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 1032 PINCTRL_CONF_DESC(9, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 1033 PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), 1034 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), 1035 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), 1036 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), 1037 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), 1038 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), 1039 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), 1040 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), 1041 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), 1042 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), 1043 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), 1044 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), 1045 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), 1046 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), 1047 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), 1048 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), 1049 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), 1050 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), 1051 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), 1052 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)), 1053 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), 1054 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), 1055 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), 1056 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), 1057 PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), 1058 PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), 1059 PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), 1060 PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), 1061 PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 1062 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 1063 }; 1064 1065 static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { 1066 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 1067 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 1068 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 1069 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 1070 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 1071 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 1072 PINCTRL_CONF_DESC(8, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 1073 PINCTRL_CONF_DESC(9, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 1074 PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), 1075 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), 1076 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), 1077 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), 1078 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), 1079 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), 1080 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), 1081 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), 1082 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), 1083 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), 1084 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), 1085 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), 1086 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), 1087 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), 1088 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), 1089 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), 1090 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), 1091 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), 1092 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), 1093 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)), 1094 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), 1095 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), 1096 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), 1097 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), 1098 PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), 1099 PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), 1100 PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), 1101 PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), 1102 PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 1103 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 1104 }; 1105 1106 static const struct airoha_pinctrl_match_data pinctrl_match_data = { 1107 .chip_scu_compatible = "airoha,en7523-chip-scu", 1108 .pinctrl_name = KBUILD_MODNAME, 1109 .pinctrl_owner = THIS_MODULE, 1110 .pins = pinctrl_pins, 1111 .num_pins = ARRAY_SIZE(pinctrl_pins), 1112 .grps = pinctrl_groups, 1113 .num_grps = ARRAY_SIZE(pinctrl_groups), 1114 .funcs = pinctrl_funcs, 1115 .num_funcs = ARRAY_SIZE(pinctrl_funcs), 1116 .confs_info = { 1117 [AIROHA_PINCTRL_CONFS_PULLUP] = { 1118 .confs = pinctrl_pullup_conf, 1119 .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), 1120 }, 1121 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 1122 .confs = pinctrl_pulldown_conf, 1123 .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), 1124 }, 1125 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 1126 .confs = pinctrl_drive_e2_conf, 1127 .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), 1128 }, 1129 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 1130 .confs = pinctrl_drive_e4_conf, 1131 .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), 1132 }, 1133 }, 1134 }; 1135 1136 static const struct of_device_id airoha_pinctrl_of_match[] = { 1137 { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data }, 1138 { /* sentinel */ } 1139 }; 1140 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); 1141 1142 static struct platform_driver airoha_pinctrl_driver = { 1143 .probe = airoha_pinctrl_probe, 1144 .driver = { 1145 .name = "pinctrl-airoha-en7523", 1146 .of_match_table = airoha_pinctrl_of_match, 1147 }, 1148 }; 1149 module_platform_driver(airoha_pinctrl_driver); 1150 1151 MODULE_LICENSE("GPL"); 1152 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 1153 MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); 1154 MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); 1155 MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>"); 1156 MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>"); 1157 MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC"); 1158