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/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
200 * so the center channel is 30 channels away from the start/end. in get_center_320mhz()
202 if (channel >= center_channels[i] - 30 && in get_center_320mhz()
203 channel <= center_channels[i] + 30) in get_center_320mhz()
232 u8 adj_chan = center_chan - 30 + i * 4; in verify_320mhz()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
174 at24@30 {
262 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
263 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h43 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30),
370 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30)
585 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30)
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h82 * Kiwi only, bit 30 is used to set the error type, if set it is 0x5 (HAL_PHYERR_RADAR)
86 #define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI_S 30 /* Spectral Error select bit 30 */
89 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_SELECT_KIWI_S 29 /* Spectral Error select bit 30 */
122 #define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
133 …AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
134 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz…
/freebsd/contrib/wpa/src/common/
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pri/sec mismatch with BSS " in check_40mhz_2g4()
373 "40 MHz Intolerant is set on channel %d in BSS " in check_40mhz_2g4()
449 /* TODO: 320 MHz */ in punct_update_legacy_bw()
547 "6 GHz 80+80 MHz configuration doesn't use valid 80 MHz channels"); in hostapd_set_freq_params()
[all …]
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
1721 case 25: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
1722 case 26: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Drockchip,dwc3.txt8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
H A Drockchip,dwc3.yaml53 Controller reference clock, must to be 24 MHz
55 Controller suspend clock, must to be 24 MHz or 32 KHz
57 Master/Core clock, must to be >= 62.5 MHz for SS
58 operation and >= 30MHz for HS operation
H A Drockchip,rk3399-dwc3.yaml27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Duncore-power.json10 …uency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can als…
20 …uency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can als…
30 …uency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can als…
40 …uency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can als…
50 …uency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can als…
61 …uency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can als…
72 …uency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can als…
83 …uency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can als…
213 "Filter": "filter_band2=30",
257 "Filter": "edge=1,filter_band2=30",
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Duncore-power.json10 …quency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can als…
20 …quency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can als…
30 …quency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can als…
40 …uency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can als…
50 …quency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can als…
61 …quency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can als…
72 …quency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can als…
83 …uency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can als…
212 "Filter": "filter_band2=30",
256 "Filter": "edge=1,filter_band2=30",
/freebsd/sys/contrib/dev/iwlwifi/cfg/
H A D9000.c16 #define IWL9000_UCODE_API_MIN 30
163 const char iwl9162_160_name[] = "Intel(R) Wireless-AC 9162 160MHz";
164 const char iwl9260_160_name[] = "Intel(R) Wireless-AC 9260 160MHz";
165 const char iwl9270_160_name[] = "Intel(R) Wireless-AC 9270 160MHz";
166 const char iwl9461_160_name[] = "Intel(R) Wireless-AC 9461 160MHz";
167 const char iwl9462_160_name[] = "Intel(R) Wireless-AC 9462 160MHz";
168 const char iwl9560_160_name[] = "Intel(R) Wireless-AC 9560 160MHz";
171 "Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz";
175 "Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz";
179 "Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz";
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c78 #define PLL_BASE_ENABLE (1 << 30)
88 #define PLLC4_LOCK_ENABLE (1 << 30)
90 #define PLLD2_LOCK_ENABLE (1 << 30)
92 #define PLLREFE_LOCK_ENABLE (1 << 30)
93 #define PLLPD_LOCK_ENABLE (1 << 30)
264 {30, 15},
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
306 /* PLLC: 510 MHz Clock source for camera use */
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c67 #define PLL_BASE_ENABLE (1 << 30)
78 #define PLLRE_MISC_LOCK_ENABLE (1 << 30)
79 #define PLLSS_MISC_LOCK_ENABLE (1 << 30)
131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
216 /* PLLM: 880 MHz Clock source for EMC 2x clock */
240 /* PLLC: 600 MHz Clock source for general use */
253 /* PLLC2: 600 MHz Clock source for engine scaling */
264 /* PLLC3: 600 MHz Clock source for engine scaling */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz widt
[all...]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c393 #define IV_KEYID(iv) (((iv) >> 30) & 0x03)
430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
446 { /* 20 Mhz */ { 19.5f, /* SGI */ 21.7f, },
447 /* 40 Mhz */ { 40.5f, /* SGI */ 45.0f, },
451 { /* 20 Mhz */ { 26.0f, /* SGI */ 28.9f, },
452 /* 40 Mhz */ { 54.0f, /* SGI */ 60.0f, },
[all …]
/freebsd/sys/net80211/
H A Dieee80211_dfs.c56 static int ieee80211_nol_timeout = 30*60; /* 30 minutes */
148 "CAC timer on channel %u (%u MHz) stopped due to radar\n", in cac_timeout()
157 "CAC timer on channel %u (%u MHz) expired; " in cac_timeout()
191 "start %d second CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_start()
211 "stop CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_stop()
255 "(%u MHz) cleared after timeout\n", in dfs_timeout()
277 ic_printf(ic, "radar detected on channel %u (%u MHz)\n", in announce_radar()
280 ic_printf(ic, "radar detected on channel %u (%u MHz), " in announce_radar()
281 "moving to channel %u (%u MHz)\n", in announce_radar()
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,quadfs.txt5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
/freebsd/sys/contrib/dev/athk/ath11k/
H A Ddebugfs_htt_stats.h45 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30,
253 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are
257 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
467 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
505 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
623 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins
627 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
1263 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1353 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
1620 * 30 phyrx_err_vht_rx_extra_symbol_mismatch
[all …]
/freebsd/sys/contrib/device-tree/src/mips/realtek/
H A Drtl930x.dtsi21 baseclk: clock-800mhz {
27 lx_clk: clock-175mhz {
69 interrupts = <30>;
/freebsd/sys/dev/ffec/
H A Dif_ffecreg.h44 #define FEC_IER_BABR (1 << 30)
79 #define FEC_MMFR_ST_SHIFT 30
102 #define FEC_MIBC_IDLE (1 << 30)
107 #define FEC_RCR_NLC (1 << 30)
268 #define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */
290 #define FEC_TXDESC_T01 (1 << 30)
299 #define FEC_RXDESC_R01 (1 << 30)
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
73 - description: CK_SCMI_FLEXGEN_30 flexgen clock 30
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-r1.dts102 capacity-dmips-mhz = <1024>;
119 capacity-dmips-mhz = <1024>;
136 capacity-dmips-mhz = <578>;
153 capacity-dmips-mhz = <578>;
170 capacity-dmips-mhz = <578>;
187 capacity-dmips-mhz = <578>;
222 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
H A Djuno-r2.dts102 capacity-dmips-mhz = <1024>;
120 capacity-dmips-mhz = <1024>;
138 capacity-dmips-mhz = <485>;
156 capacity-dmips-mhz = <485>;
174 capacity-dmips-mhz = <485>;
192 capacity-dmips-mhz = <485>;
228 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
H A Djuno.dts101 capacity-dmips-mhz = <1024>;
119 capacity-dmips-mhz = <1024>;
137 capacity-dmips-mhz = <578>;
155 capacity-dmips-mhz = <578>;
173 capacity-dmips-mhz = <578>;
191 capacity-dmips-mhz = <578>;
227 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

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