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/linux/drivers/tty/serial/
H A Ddz.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
39 #define LINE(x) ((x & DZ_LINE_MASK) >> 8) /* Get the line number macro
51 #define DZ_MODEM_RTS 0x0800 /* RTS for the modem line (2) */
52 #define DZ_MODEM_DTR 0x0400 /* DTR for the modem line (2) */
53 #define DZ_PRINT_RTS 0x0200 /* RTS for the prntr line (3) */
54 #define DZ_PRINT_DTR 0x0100 /* DTR for the prntr line (3) */
55 #define DZ_LNENB 0x000f /* Transmitter Line Enable */
60 #define DZ_MODEM_RI 0x0800 /* RI for the modem line (2) */
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/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
[all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dcache.json4 "Counter": "0,1,2,3",
11 …ription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
12 "Counter": "0,1,2,3",
20 "Counter": "0,1,2,3",
27 "BriefDescription": "L1D data line replacements.",
28 "Counter": "0,1,2,3",
31 …event counts L1D data line replacements. Replacements occur when a new line is brought into the c…
37 "Counter": "0,1,2,3",
46 "Counter": "0,1,2,3",
82 "Counter": "0,1,2,3",
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/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A Dfrontend.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
31 "Counter": "0,1,2,3",
39 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
40 "Counter": "0,1,2,3",
43 …Line. The event strives to count on a cache line basis, so that multiple fetches to a single cach…
48 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
49 "Counter": "0,1,2,3",
52 …Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis…
[all …]
H A Dcache.json4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
15 …ed (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. N…
20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
38 "Counter": "0,1,2,3",
47 "Counter": "0,1,2,3",
50 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
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/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A Dfrontend.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
31 "Counter": "0,1,2,3",
39 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
40 "Counter": "0,1,2,3",
43 …Line. The event strives to count on a cache line basis, so that multiple fetches to a single cach…
48 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
49 "Counter": "0,1,2,3",
52 …Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis…
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/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dfrontend.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
45 "Counter": "0,1,2,3",
52 …": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
53 "Counter": "0,1,2,3",
56 …line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk co…
62 "Counter": "0,1,2,3",
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dfrontend.json4 "Counter": "0,1,2,3",
13 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
29 "Counter": "0,1,2,3",
37 "Counter": "0,1,2,3",
45 "Counter": "0,1,2,3",
52 …": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
53 "Counter": "0,1,2,3",
56 …line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk co…
62 "Counter": "0,1,2,3",
[all …]
/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
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H A Dsys_noritake.c1 // SPDX-License-Identifier: GPL-2.0
52 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); in noritake_enable_irq()
58 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); in noritake_disable_irq()
86 pld &= pld - 1; /* clear least bit set */ in noritake_device_interrupt()
100 irq = (vector - 0x800) >> 4; in noritake_srm_device_interrupt()
109 * So, here's this additional grotty hack... :-( in noritake_srm_device_interrupt()
144 * 0 All valid ints from summary regs 2 & 3
146 * 2 Interrupt Line A from slot 0
147 * 3 Interrupt Line B from slot 0
148 * 4 Interrupt Line A from slot 1
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H A Dsys_sx164.c1 // SPDX-License-Identifier: GPL-2.0
49 /* Not interested in the bogus interrupts (0,3,4,5,40-47), in sx164_init_irq()
56 if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) in sx164_init_irq()
57 pr_err("Failed to register timer-cascade interrupt\n"); in sx164_init_irq()
68 * 3 MBZ
72 * 7 PCI-ISA Bridge
73 * 8 Interrupt Line A from slot 3
74 * 9 Interrupt Line A from slot 2
75 *10 Interrupt Line A from slot 1
76 *11 Interrupt Line A from slot 0
[all …]
H A Dsys_rawhide.c1 // SPDX-License-Identifier: GPL-2.0
61 unsigned int irq = d->irq; in rawhide_enable_irq()
63 irq -= 16; in rawhide_enable_irq()
65 if (!hose_exists(hose)) /* if hose non-existent, exit */ in rawhide_enable_irq()
68 irq -= hose * 24; in rawhide_enable_irq()
82 unsigned int irq = d->irq; in rawhide_disable_irq()
84 irq -= 16; in rawhide_disable_irq()
86 if (!hose_exists(hose)) /* if hose non-existent, exit */ in rawhide_disable_irq()
89 irq -= hose * 24; in rawhide_disable_irq()
103 unsigned int irq = d->irq; in rawhide_mask_and_ack_irq()
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Dcache.json3 "BriefDescription": "L1D data line replacements",
4 "Counter": "0,1,2,3",
7 … "Counts L1D data line replacements including opportunistic replacements, and replacements that re…
13 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
25 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
31 "Counter": "0,1,2,3",
42 "Counter": "0,1,2,3",
51 "Counter": "0,1,2,3",
60 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
24 "Unit": "CPU-M-CF",
28 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
31 "Unit": "CPU-M-CF",
35 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-lenovo-hr855xg2.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
[all …]
H A Daspeed-bmc-lenovo-hr630.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dcache.json4 "Counter": "0,1,2,3",
11 …ription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
12 "Counter": "0,1,2,3",
20 "Counter": "0,1,2,3",
27 "BriefDescription": "L1D data line replacements.",
28 "Counter": "0,1,2,3",
31 …event counts L1D data line replacements. Replacements occur when a new line is brought into the c…
37 "Counter": "0,1,2,3",
46 "Counter": "0,1,2,3",
82 "Counter": "0,1,2,3",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-vbi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-vbi.c
10 #include "cx18-driver.h"
11 #include "cx18-vbi.h"
12 #include "cx18-ioctl.h"
13 #include "cx18-queue.h"
18 * of VBI sample or VBI ancillary data regions in the digital ratser line.
27 int line = 0; in copy_vbi_data() local
32 /* MPEG-2 Program Pack */ in copy_vbi_data()
37 /* MPEG-2 Private Stream 1 PES Packet */ in copy_vbi_data()
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/linux/drivers/gpio/
H A Dgpio-ts5500.c1 // SPDX-License-Identifier: GPL-2.0
3 * Digital I/O driver for Technologic Systems TS-5500
5 * Copyright (c) 2012 Savoir-faire Linux Inc.
10 * In that sense, the support is not limited to the TS-5500 blocks.
13 * TS-5500:
14 * Documentation: https://docs.embeddedts.com/TS-5500
17 * TS-5600:
18 * Documentation: https://docs.embeddedts.com/TS-5600
19 * Blocks: LCD port (identical to TS-5500 LCD).
99 TS5500_DIO_IN_OUT(vaddr, vbitfrom + 3, caddr, cbit)
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/linux/Documentation/gpu/amdgpu/display/
H A Dconfig_example.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
7 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
10 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
17 inkscape:version="0.92.5 (2060ec1f9f, 2020-04-08)"
31 d="M 0,0 5,-5 -12.5,0 5,5 Z"
32 …style="fill:#ff0000;fill-opacity:1;fill-rule:evenodd;stroke:#ff0000;stroke-width:1.00000003pt;stro…
33 transform="matrix(-0.4,0,0,-0.4,-4,0)"
34 inkscape:connector-curvature="0" />
41 id="Arrow1Mend-3"
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c1 // SPDX-License-Identifier: GPL-2.0
16 #define IDLE_CHK_WARNING 3
30 u32 imm1; /* 1st value in predicate condition, left-to-right */
31 u32 imm2; /* 2nd value in predicate condition, left-to-right */
32 u32 imm3; /* 3rd value in predicate condition, left-to-right */
33 u32 imm4; /* 4th value in predicate condition, left-to-right */
36 /* struct representing self test record - a single test */
54 return (args->val1 == args->imm1); in peq()
59 return (args->val1 != args->imm1); in pneq()
64 return ((args->val1 & args->imm1) != args->imm2); in pand_neq()
[all …]
/linux/drivers/media/pci/ivtv/
H A Divtv-vbi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 Copyright (C) 2004-2007 Hans Verkuil <hverkuil@xs4all.nl>
8 #include "ivtv-driver.h"
9 #include "ivtv-i2c.h"
10 #include "ivtv-ioctl.h"
11 #include "ivtv-queue.h"
12 #include "ivtv-cards.h"
13 #include "ivtv-vbi.h"
19 if (!(itv->v4l2_cap & V4L2_CAP_VIDEO_OUTPUT)) in ivtv_set_vps()
23 data.line = enabled ? 16 : 0; in ivtv_set_vps()
[all …]
/linux/sound/soc/codecs/
H A Dwm8750.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8750.c -- WM8750 ALSA SoC audio driver
39 { 3, 0x0079 },
100 static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
102 static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
106 static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
145 SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
158 SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
160 SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
161 SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
[all …]

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