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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
15 - compatible : compatible list, contains 2 entries, first is
45 Supported values are: "mii", "rmii", "smii", "rgmii",
47 For Axon on CAB, it is "rgmii"
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
57 For Axon: phandle of plb5/plb4/opb/rgmii
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
143 phy-mode = "rgmii";
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
33 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
57 drive strength of rx_clk rgmii pa
[all...]
H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
55 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
61 enum: [0, 2, 4, 6]
62 default: 2
64 The internal RGMII TX clock delay (provided by this driver)
65 in nanoseconds. When phy-mode is set to "rgmii" then the TX
67 set to either "rgmii-id" or "rgmii-txid" the TX clock delay
78 - 2
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
175 phy-mode = "rgmii";
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
112 1. tx clock will be inversed in MII/RGMII case,
113 2. tx clock inside MAC will be inversed relative to reference clock
122 1. rx clock will be inversed in MII/RGMII case.
123 2. reference clock will be inversed when arrived at MAC in RMII case, when
159 phy-mode = "rgmii
[all...]
H A Dmediatek-dwmac.txt25 It should be defined for RGMII/MII interface.
28 It should be defined for RGMII/MII interface.
30 Both delay properties need to be a multiple of 170 for RGMII interface,
42 1. tx clock will be inversed in MII/RGMII case,
43 2. tx clock inside MAC will be inversed relative to reference clock
48 1. rx clock will be inversed in MII/RGMII case.
49 2. reference clock will be inversed when arrived at MAC in RMII case, when
62 phy-mode ="rgmii-rxid";
H A Dqcom,ethqos.txt16 - reg-names: Should contain register names "stmmaceth", "rgmii"
21 "ptp_ref", "rgmii"
36 reg-names = "stmmaceth", "rgmii";
37 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
49 snps,rxpbl = <2>;
54 phy-mode = "rgmii";
H A Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
28 maxItems: 2
33 - const: rgmii
58 - rgmii
89 reg-names = "stmmaceth", "rgmii";
90 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
112 phy-mode = "rgmii";
H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
37 - const: tx0-2
41 - const: tx1-2
68 maxItems: 2
75 maxItems: 2
110 ti,syscon-rgmii-delay:
118 to ICSSG control register for RGMII transmit delay
185 ti,pruss-gp-mux-sel = <2>, /* MII mode */
186 <2>,
187 <2>,
[all …]
H A Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
31 - const: txrx-2
56 - rgmii
57 - rgmii-id
79 #address-cells = <2>;
80 #size-cells = <2>;
87 phy-mode = "rgmii";
104 interrupt-names = "mac", "txrx-1", "txrx-2", "txrx-3";
107 phy-mode = "rgmii";
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
97 should use "rgmii-id" if internal delays are desired as this may be
98 changed in future to cause "rgmii" mode to disable delays.
104 mode 1 or 2. To ensure PHY operation, there are specific actions that
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
33 clock source or sink for this interface (not applicable for RGMII
35 - In the case of RGMII it affects the behavior regarding internal
38 of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity
39 designated to apply the delay/clock skew necessary for RGMII
41 2. If sja1105,role-phy is specified, and the phy-mode property is one
45 E or T device, it is an error to specify an RGMII phy-mode other
46 than "rgmii" for a port that is in fixed-link mode. In that case,
88 phy-mode = "rgmii-id";
96 phy-mode = "rgmii-id";
[all …]
H A Dmt7530.txt39 must be either "trgmii" or "rgmii"
45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
47 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
58 and RGMII delay.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64 Currently a 2nd CPU port is not supported by DSA code.
67 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
[all …]
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
38 # Optional container node for the 2 internal MDIO buses of the SJA1110
42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
87 - rgmii
88 - rgmii-rxid
89 - rgmii-txid
90 - rgmii-id
156 phy-mode = "rgmii-id";
164 phy-mode = "rgmii-id";
170 port@2 {
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H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
49 - rgmii
50 - rgmii-id
51 - rgmii-txid
52 - rgmii-rxid
109 port@2 {
110 reg = <2>;
125 phy-mode = "rgmii";
139 phy-mode = "rgmii";
176 t1phy2: ethernet-phy@2{
[all...]
H A Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 RGMII ports and one RMII port and are managed via i2c or mdio.
54 phy-mode = "rgmii-id";
56 ethernet-port@2 {
57 reg = <2>;
60 phy-mode = "rgmii-id";
65 phy-mode = "rgmii-id";
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Deiger.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
60 #interrupt-cells = <2>;
70 #interrupt-cells = <2>;
78 cell-index = <2>;
82 #interrupt-cells = <2>;
94 #interrupt-cells = <2>;
111 #address-cells = <2>;
154 #address-cells = <2>;
163 bank-width = <2>;
[all …]
H A Dglacier.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
61 #interrupt-cells = <2>;
71 #interrupt-cells = <2>;
79 cell-index = <2>;
83 #interrupt-cells = <2>;
95 #interrupt-cells = <2>;
122 #address-cells = <2>;
171 #address-cells = <2>;
180 bank-width = <2>;
[all …]
H A Dklondike.dts54 #interrupt-cells = <2>;
64 #interrupt-cells = <2>;
72 cell-index = <2>;
76 #interrupt-cells = <2>;
88 #interrupt-cells = <2>;
108 num-tx-chans = <2>;
131 RGMII0: emac-rgmii@400a2000 {
132 compatible = "ibm,rgmii";
164 phy-mode = "rgmii";
168 rgmii-device = <&RGMII0>;
[all …]
H A Drainier.dts10 * License version 2. This program is licensed "as is" without
18 #address-cells = <2>;
64 #interrupt-cells = <2>;
74 #interrupt-cells = <2>;
82 cell-index = <2>;
86 #interrupt-cells = <2>;
103 #address-cells = <2>;
121 num-tx-chans = <2>;
122 num-rx-chans = <2>;
149 #address-cells = <2>;
[all …]
H A Dobs600.dts11 * License version 2. This program is licensed "as is" without
62 #interrupt-cells = <2>;
72 #interrupt-cells = <2>;
80 cell-index = <2>;
84 #interrupt-cells = <2>;
123 num-tx-chans = <2>;
124 num-rx-chans = <2>;
151 #address-cells = <2>;
160 bank-width = <2>;
238 RGMII0: emac-rgmii@ef600b00 {
[all …]
H A Dfsp2.dts7 * License version 2. This program is licensed "as is" without
15 #address-cells = <2>;
64 #interrupt-cells = <2>;
76 #interrupt-cells = <2>;
90 #interrupt-cells = <2>;
94 cell-index = <2>;
104 #interrupt-cells = <2>;
118 #interrupt-cells = <2>;
131 #interrupt-cells = <2>;
144 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tsn.dts27 reg_vddio_codec: regulator-2V5 {
29 regulator-name = "2P5V";
62 phy-mode = "rgmii-id";
70 phy-mode = "rgmii-id";
74 port@2 {
78 phy-mode = "rgmii-id";
79 reg = <2>;
86 phy-mode = "rgmii-id";
93 phy-mode = "rgmii";
121 /* RGMII delays added via PCB traces */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am654-idk.dtso37 ti,pruss-gp-mux-sel = <2>, /* MII mode */
38 <2>,
39 <2>,
40 <2>, /* MII mode */
41 <2>,
42 <2>;
49 interrupts = <24 0 2>, <25 1 3>;
63 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
64 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
73 phy-mode = "rgmii-id";
[all …]
/freebsd/sys/dev/etherswitch/arswitch/
H A Darswitch_8316.c2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
76 * + The switch port is GMII/RGMII; in ar8316_hw_setup()
83 "%s: MAC port == RGMII, port 4 = dedicated PHY\n", in ar8316_hw_setup()
89 "%s: MAC port == RGMII, port 4 = switch port\n", in ar8316_hw_setup()
104 * If port 4 is RGMII, force workaround in ar8316_hw_setup()
108 "%s: port 4 RGMII workaround\n", in ar8316_hw_setup()
111 /* work around for phy4 rgmii mode */ in ar8316_hw_setup()
150 AR8316_GLOBAL_CTRL_MTU_MASK, 9018 + 8 + 2); in ar8316_hw_global_setup()

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