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/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
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H A Dmt76x02_dma.h1 /* SPDX-License-Identifier: ISC */
13 #define MT_TXD_INFO_NEXT_VLD BIT(16)
14 #define MT_TXD_INFO_TX_BURST BIT(17)
15 #define MT_TXD_INFO_80211 BIT(19)
16 #define MT_TXD_INFO_TSO BIT(20)
17 #define MT_TXD_INFO_CSO BIT(21)
18 #define MT_TXD_INFO_WIV BIT(24)
20 #define MT_TXD_INFO_DPORT GENMASK(29, 27)
24 #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
27 #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
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/linux/drivers/media/pci/zoran/
H A Dzr36057.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
14 #define ZR36057_VFEHCR_HS_POL BIT(30)
20 #define ZR36057_VFEVCR_VS_POL BIT(30)
26 #define ZR36057_VFESPFR_EXT_FL BIT(26)
27 #define ZR36057_VFESPFR_TOP_FIELD BIT(25)
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
37 #define ZR36057_VFESPFR_ERR_DIF BIT(2)
38 #define ZR36057_VFESPFR_PACK24 BIT(1)
39 #define ZR36057_VFESPFR_LITTLE_ENDIAN BIT(0)
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
35 #define CIWDOFST_WINOFSEN BIT(31)
36 #define CIWDOFST_CLROVCOFIY BIT(30)
37 #define CIWDOFST_CLROVRLB_PR BIT(28)
38 /* #define CIWDOFST_CLROVPRFIY BIT(27) */
39 #define CIWDOFST_CLROVCOFICB BIT(15)
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/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
34 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
39 #define BFPT_DWORD1_DTR BIT(19)
40 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
41 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
42 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
45 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
46 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
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/linux/drivers/net/ethernet/airoha/
H A Dairoha_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define FE_DMA_GLO_PG_SZ_MASK BIT(3)
36 #define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
37 #define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
38 #define FE_RST_CORE_MASK BIT(0)
43 #define WAN1_EN_MASK BIT(16)
59 #define PCE_DPI_EN_MASK BIT(2)
60 #define PCE_KA_EN_MASK BIT(1)
61 #define PCE_MC_EN_MASK BIT(0)
66 #define PSE_CFG_WR_EN_MASK BIT(8)
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/linux/drivers/net/ipa/reg/
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
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H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
29 #define AHB_IDLE_EN_EXT_SFT 29
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
78 # define V3D_INT_SPILLUSE BIT(3)
79 # define V3D_INT_OUTOMEM BIT(2)
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/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_gpu_commands.h1 /* SPDX-License-Identifier: MIT */
11 #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
21 #define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
28 #define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
34 #define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
42 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
44 #define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
45 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
47 #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
51 #define PIPE_CONTROL_LRI_POST_SYNC BIT(23)
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/linux/drivers/media/platform/nxp/dw100/
H A Ddw100_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define DW100_DEWARP_CTRL_ENABLE BIT(0)
16 #define DW100_DEWARP_CTRL_START BIT(1)
17 #define DW100_DEWARP_CTRL_SOFT_RESET BIT(2)
25 #define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW BIT(8)
26 #define DW100_DEWARP_CTRL_HW_HANDSHAKE BIT(9)
27 #define DW100_DEWARP_CTRL_DST_AUTO_SHADOW BIT(10)
28 #define DW100_DEWARP_CTRL_SPLIT_LINE BIT(11)
37 #define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))
42 #define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))
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/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
29 #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
34 #define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
35 #define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
38 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
40 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
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/linux/drivers/usb/chipidea/
H A Dbits.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bits.h - register bits of the ChipIdea USB IP core
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 * For 1.x revision, bit24 - bit31 are reserved
18 * For 2.x revision, bit25 - bit28 are 0x2
23 #define CIVERSION (0x7 << 29)
29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
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/linux/drivers/media/platform/ti/cal/
H A Dcal_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m) BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m) BIT(m)
[all …]
/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
18 * for the MAILBOX structure. Software must poll the ready bit until this
20 * bits in the address. It must poll the ready bit until the command is
25 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
40 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-mtd3 KernelVersion: 2.6.29
4 Contact: linux-mtd@lists.infradead.org
11 KernelVersion: 2.6.29
12 Contact: linux-mtd@lists.infradead.org
21 KernelVersion: 2.6.29
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
29 KernelVersion: 2.6.29
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
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/linux/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
200 #define GMAC1_TXDERR_INT_BIT BIT(31)
201 #define GMAC1_TXPERR_INT_BIT BIT(30)
202 #define GMAC0_TXDERR_INT_BIT BIT(29)
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/linux/include/sound/sof/ipc4/
H A Dheader.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
24 * struct sof_ipc4_msg - Placeholder of an IPC4 message
46 * struct sof_ipc4_tuple - Generic type/ID and parameter tuple
58 * IPC4 messages have two 32 bit identifier made up as follows :-
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/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
53 #define OPCR_SPENDN0 BIT(7)
54 #define OPCR_SPENDN1 BIT(6)
57 #define USBPCR_USB_MODE BIT(31)
59 #define USBPCR_COMMONONN BIT(25)
60 #define USBPCR_VBUSVLDEXT BIT(24)
61 #define USBPCR_VBUSVLDEXTSEL BIT(23)
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