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/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
[all …]
/linux/drivers/media/pci/zoran/
H A Dzr36057.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
14 #define ZR36057_VFEHCR_HS_POL BIT(30)
20 #define ZR36057_VFEVCR_VS_POL BIT(30)
26 #define ZR36057_VFESPFR_EXT_FL BIT(26)
27 #define ZR36057_VFESPFR_TOP_FIELD BIT(25)
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
37 #define ZR36057_VFESPFR_ERR_DIF BIT(2)
38 #define ZR36057_VFESPFR_PACK24 BIT(1)
39 #define ZR36057_VFESPFR_LITTLE_ENDIAN BIT(0)
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
35 #define CIWDOFST_WINOFSEN BIT(31)
36 #define CIWDOFST_CLROVCOFIY BIT(30)
37 #define CIWDOFST_CLROVRLB_PR BIT(28)
38 /* #define CIWDOFST_CLROVPRFIY BIT(27) */
39 #define CIWDOFST_CLROVCOFICB BIT(15)
[all …]
/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
34 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
39 #define BFPT_DWORD1_DTR BIT(19)
40 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
41 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
42 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
45 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
46 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
23 [GSI_SNOC_BYPASS_DIS] = BIT(1),
24 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
25 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
26 /* Bit 4 reserved */
27 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
28 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 /* Bit 4 reserved */
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 /* Bit 0 reserved */
14 [GSI_SNOC_BYPASS_DIS] = BIT(1),
15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
18 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
19 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
29 #define AHB_IDLE_EN_EXT_SFT 29
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
78 # define V3D_INT_SPILLUSE BIT(3)
79 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/linux/drivers/media/platform/nxp/dw100/
H A Ddw100_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define DW100_DEWARP_CTRL_ENABLE BIT(0)
16 #define DW100_DEWARP_CTRL_START BIT(1)
17 #define DW100_DEWARP_CTRL_SOFT_RESET BIT(2)
25 #define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW BIT(8)
26 #define DW100_DEWARP_CTRL_HW_HANDSHAKE BIT(9)
27 #define DW100_DEWARP_CTRL_DST_AUTO_SHADOW BIT(10)
28 #define DW100_DEWARP_CTRL_SPLIT_LINE BIT(11)
37 #define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0))
42 #define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0))
[all …]
/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
29 #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
34 #define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
35 #define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
38 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
40 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
[all …]
/linux/drivers/usb/chipidea/
H A Dbits.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bits.h - register bits of the ChipIdea USB IP core
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 * For 1.x revision, bit24 - bit31 are reserved
18 * For 2.x revision, bit25 - bit28 are 0x2
23 #define CIVERSION (0x7 << 29)
29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
[all …]
/linux/drivers/media/platform/ti/cal/
H A Dcal_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
128 #define CAL_HL_IRQ_WDMA_END_MASK(m) BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m) BIT(m)
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-mtd3 KernelVersion: 2.6.29
4 Contact: linux-mtd@lists.infradead.org
11 KernelVersion: 2.6.29
12 Contact: linux-mtd@lists.infradead.org
21 KernelVersion: 2.6.29
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
29 KernelVersion: 2.6.29
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
[all …]
/linux/drivers/net/ethernet/cortina/
H A Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
200 #define GMAC1_TXDERR_INT_BIT BIT(31)
201 #define GMAC1_TXPERR_INT_BIT BIT(30)
202 #define GMAC0_TXDERR_INT_BIT BIT(29)
[all …]
/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
53 #define OPCR_SPENDN0 BIT(7)
54 #define OPCR_SPENDN1 BIT(6)
57 #define USBPCR_USB_MODE BIT(31)
59 #define USBPCR_COMMONONN BIT(25)
60 #define USBPCR_VBUSVLDEXT BIT(24)
61 #define USBPCR_VBUSVLDEXTSEL BIT(23)
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
19 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
20 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
25 #define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
34 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31)
35 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30)
36 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29)
37 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28)
40 #define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23)
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
77 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
81 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8812a.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
26 rx_pwr_all = -94 + 2 * (27 - vga_idx); in rtw8812a_cck_rx_pwr()
28 rx_pwr_all = -94; in rtw8812a_cck_rx_pwr()
31 rx_pwr_all = -42 + 2 * (2 - vga_idx); in rtw8812a_cck_rx_pwr()
34 rx_pwr_all = -36 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
37 rx_pwr_all = -30 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
40 rx_pwr_all = -18 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
43 rx_pwr_all = 2 * (5 - vga_idx); in rtw8812a_cck_rx_pwr()
46 rx_pwr_all = 14 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
49 rx_pwr_all = 20 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-dp.c1 // SPDX-License-Identifier: GPL-2.0
20 #define TPLL_SSC_EN BIT(3)
29 #define DP_GLB_SW_RST_PHYD BIT(0)
35 #define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
36 #define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
38 #define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29)
46 #define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21))
47 #define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29)
53 #define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5))
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
16 #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
17 #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
29 #define MTK_WED_RESET_TX_BM BIT(0)
[all …]

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