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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dbrcm,brcmstb-waketimer.txt3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
10 - clocks : The phandle to the UPG fixed clock (27Mhz domain)
H A Dbrcm,brcmstb-waketimer.yaml13 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
38 description: clock reference in the 27MHz domain
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz widt
[all...]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dsony,imx412.yaml34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
H A Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
H A Dsony,imx334.yaml32 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
H A Dsony,imx335.yaml32 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dti,sn65dsi86.txt29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
H A Dti,sn65dsi86.yaml56 be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_misc.c95 * baseband registers (27-31, 124-127) are required.
103 * and also enable turning OFF 32MHz/40MHz Refclk in ar5312SetupClock()
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312SetupClock()
139 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
145 /* # Set sleep clock rate back to 32 MHz. */ in ar5312RestoreClock()
146 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312RestoreClock()
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
195 interrupts = <27>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmediatek,xsphy.yaml68 mediatek,src-ref-clk-mhz:
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
176 mediatek,src-ref-clk-mhz = <26>;
H A Dphy-mtk-xsphy.txt21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
38 24M, 25M or 27M, depended on platform.
88 mediatek,src-ref-clk-mhz = <26>;
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h40 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27),
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
794 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
798 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
98 &gpio_pic 27 0 /* done */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
257 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c80 #define PLL_BASE_LOCK (1 << 27)
82 #define PLLREFE_MISC_LOCK (1 << 27)
98 #define PLLC_IDDQ_BIT 27
102 #define PLLA1_IDDQ_BIT 27
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
306 /* PLLC: 510 MHz Clock source for camera use */
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
339 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam5729-beagleboneai.dts79 gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
423 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
534 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
556 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
557 /* HS: High speed up to 50 MHz (3.3 V signaling). */
558 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
559 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
560 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
561 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
562 /* DDR50: DDR up to 50 MHz (1.
[all...]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c205 27, /* gate */
218 27, /* gate */
222 /* PLL_PERIPH(4X) = 24 MHz * N / M1 / M0 */
232 27, /* gate */
236 /* PLL_PERIPH0(2X) = 24 MHz * N / M / P0 */
248 /* PLL_PERIPH0(800M) = 24 MHz * N / M / P1 */
260 /* PLL_PERIPH0(1X) = 24 MHz * N / M / P0 / 2 */
280 27, /* gate */
317 27, /* gate */
354 27, /* gate */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drockchip-dwmac.txt32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
34 PHY provides the reference clock(50MHz), "output" means GMAC provides the
52 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
H A Drockchip-dwmac.yaml77 For RGMII, it must be "input", means main clock(125MHz)
79 For RMII, "input" means PHY provides the reference clock(50MHz),
126 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1594 /* EDMG channels 25 - 27 */ in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
1721 case 25: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
446 { /* 20 Mhz */ { 19.5f, /* SGI */ 21.7f, },
447 /* 40 Mhz */ { 40.5f, /* SGI */ 45.0f, },
451 { /* 20 Mhz */ { 26.0f, /* SGI */ 28.9f, },
452 /* 40 Mhz */ { 54.0f, /* SGI */ 60.0f, },
456 { /* 20 Mhz */ { 39.0f, /* SGI */ 43.3f, },
[all …]
/freebsd/sys/net80211/
H A Dieee80211.h518 #define IEEE80211_ACTION_CAT_CTL_RESP_MCS_NEG 25 /* 9.6.27 Control Response MCS Negotiation */
520 #define IEEE80211_ACTION_CAT_CDMG 27 /* 9.6.28 CDMG */
788 #define IEEE80211_HTCAP_SHORTGI20 0x0020 /* Short GI in 20MHz */
789 #define IEEE80211_HTCAP_SHORTGI40 0x0040 /* Short GI in 40MHz */
800 #define IEEE80211_HTCAP_DSSSCCK40 0x1000 /* DSSS/CCK in 40MHz */
802 #define IEEE80211_HTCAP_40INTOLERANT 0x4000 /* 40MHz intolerant */
867 #define IEEE80211_HTINFO_TXWIDTH_20 0x00 /* 20MHz width */
949 IEEE80211_VHT_CHANWIDTH_USE_HT = 0, /* 20 MHz or 40 MHz */
950 IEEE80211_VHT_CHANWIDTH_80MHZ = 1, /* 80MHz */
951 IEEE80211_VHT_CHANWIDTH_160MHZ = 2, /* 160MHz */
[all …]

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