Lines Matching +full:27 +full:mhz
80 #define PLL_BASE_LOCK (1 << 27)
82 #define PLLREFE_MISC_LOCK (1 << 27)
98 #define PLLC_IDDQ_BIT 27
102 #define PLLA1_IDDQ_BIT 27
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
306 /* PLLC: 510 MHz Clock source for camera use */
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
339 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
352 /* PLLP: 408 MHz Clock source for most peripherals */
391 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
404 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */
416 /* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */
429 /* PLLREFE: 624 Mhz*/
442 /* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */
452 /* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */
1020 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */
1021 #define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */
1022 #define PLLD2_VCO_MIN 750000000 /* 750 MHz */
1106 #define PLLX_PFD_MIN 12000000LL /* 12 MHz */
1107 #define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */
1218 /* Simplified setup for 38.4 MHz clock. */
1287 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ in tegra210_pll_set_freq()
1401 * XXX Simplified UTMIP settings for 38.4MHz base clock. in config_utmi_pll()