Lines Matching +full:27 +full:mhz
205 27, /* gate */
218 27, /* gate */
222 /* PLL_PERIPH(4X) = 24 MHz * N / M1 / M0 */
232 27, /* gate */
236 /* PLL_PERIPH0(2X) = 24 MHz * N / M / P0 */
248 /* PLL_PERIPH0(800M) = 24 MHz * N / M / P1 */
260 /* PLL_PERIPH0(1X) = 24 MHz * N / M / P0 / 2 */
280 27, /* gate */
317 27, /* gate */
354 27, /* gate */
358 /* For child clocks: 24MHz * N / M1 / M0 */
368 27, /* gate */
372 /* PLL_AUDIO0(2X) = (24MHz * N / M1 / M0) / P / 2 */
383 /* PLL_AUDIO0(1X) = 24MHz * N / M1 / M0 / P / 2 */
394 /* For child clocks: 24MHz * N / M */
403 27, /* gate */
407 /* PLL_AUDIO1(DIV2) = 24MHz * N / M / P0 */
419 /* PLL_AUDIO1(DIV5) = 24MHz * N / M / P1 */