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/linux/drivers/media/platform/ti/omap3isp/
H A Dcfa_coef_table.h13 { 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
14 248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
15 247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
16 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
17 248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
18 247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248,
19 244, 0, 247, 0, 12, 27, 36, 247, 250, 0, 27, 0, 4, 250, 12, 244,
20 248, 0, 0, 0, 0, 40, 0, 0, 244, 12, 250, 4, 0, 27, 0, 250,
21 247, 36, 27, 12, 0, 247, 0, 244, 0, 0, 40, 0, 0, 0, 0, 248 },
22 { 0, 247, 0, 244, 247, 36, 27, 12, 0, 27, 0, 250, 244, 12, 250, 4,
[all …]
/linux/arch/arm/mach-davinci/
H A Dirqs.h105 #define IRQ_DA830_MPUERR 27
106 #define IRQ_DA830_IOPUERR 27
107 #define IRQ_DA830_BOOTCFGERR 27
132 #define IRQ_DA850_MPUADDRERR0 27
133 #define IRQ_DA850_MPUPROTERR0 27
134 #define IRQ_DA850_IOPUADDRERR0 27
135 #define IRQ_DA850_IOPUPROTERR0 27
136 #define IRQ_DA850_IOPUADDRERR1 27
137 #define IRQ_DA850_IOPUPROTERR1 27
138 #define IRQ_DA850_IOPUADDRERR2 27
[all …]
/linux/arch/arm/crypto/
H A Dsha1-armv4-large.S90 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
96 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
115 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
121 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
140 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
146 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
165 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
171 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
190 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
196 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dda9211.txt25 interrupts = <3 27>;
34 enable-gpios = <&gpio 27 0>;
45 interrupts = <3 27>;
54 enable-gpios = <&gpio 27 0>;
71 interrupts = <3 27>;
80 enable-gpios = <&gpio 27 0>;
89 interrupts = <3 27>;
98 enable-gpios = <&gpio 27 0>;
107 interrupts = <3 27>;
116 enable-gpios = <&gpio 27 0>;
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h75 ldq $27,56($18) \n\
91 xor $25,$27,$25 \n\
127 ldq $27,32($19) \n\
146 xor $25,$27,$27 # 7 cycles from $27 load \n\
147 stq $27,32($17) \n\
205 ldq $27,24($18) \n\
226 xor $25,$27,$27 # 8 cycles from $27 load \n\
236 xor $27,$1,$1 \n\
245 ldq $27,48($20) \n\
259 xor $25,$27,$27 # 5 cycles from $27 load \n\
[all …]
/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S80 std 27,104(1)
105 mulhdu 27,9,6
129 adde 27,27,21
155 adde 27,27,21
181 adde 27,27,21
200 adde 27,27,21
218 insrdi 12,27,51,0
264 ld 27,104(1)
283 std 27,104(1)
303 mulhdu 27,9,6
[all …]
H A Dpoly1305-p10le_64.S110 SAVE_GPR 27, 216, 1
124 SAVE_VRS 27, 112, 9
143 SAVE_VSX 27, 400, 9
159 RESTORE_VRS 27, 112, 9
178 RESTORE_VSX 27, 400, 9
197 RESTORE_GPR 27, 216, 1
225 vmulouw 15, 4, 27
239 vmulouw 10, 5, 27
249 vmulouw 11, 6, 27
261 vmulouw 12, 7, 27
[all …]
H A Dchacha-p10le-8x.S96 SAVE_GPR 27, 216, 1
110 SAVE_VRS 27, 112, 9
129 SAVE_VSX 27, 400, 9
145 RESTORE_VRS 27, 112, 9
164 RESTORE_VSX 27, 400, 9
183 RESTORE_GPR 27, 216, 1
223 vadduwm 27, 27, 31
231 vxor 23, 23, 27
271 vadduwm 27, 27, 31
281 vxor 23, 23, 27
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h70 #define VIV_FE_LOAD_STATE_HEADER_OP__SHIFT 27
89 #define VIV_FE_END_HEADER_OP__SHIFT 27
96 #define VIV_FE_NOP_HEADER_OP__SHIFT 27
109 #define VIV_FE_DRAW_2D_HEADER_OP__SHIFT 27
132 #define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__SHIFT 27
148 #define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__SHIFT 27
169 #define VIV_FE_WAIT_HEADER_OP__SHIFT 27
179 #define VIV_FE_LINK_HEADER_OP__SHIFT 27
188 #define VIV_FE_STALL_HEADER_OP__SHIFT 27
209 #define VIV_FE_CALL_HEADER_OP__SHIFT 27
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h46 #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27)
83 #define GPIO_MUX_27 BIT(27)
256 #define INT_STATUS_GPIO27 BIT(27)
278 #define INT_MASK_GPIO27 BIT(27)
441 #define GPIO_DATA_27 BIT(27)
475 #define GPIO_DATA_DIRECTION_27 BIT(27)
543 #define PANEL_DISPLAY_CTRL_FPEN BIT(27)
584 #define PANEL_FB_ADDRESS_EXT BIT(27)
662 #define VIDEO_FB_0_ADDRESS_EXT BIT(27)
670 #define VIDEO_FB_0_LAST_ADDRESS_EXT BIT(27)
[all …]
/linux/drivers/video/logo/
H A Dlogo_spe_clut224.ppm20 0 0 0 0 0 0 2 2 2 27 27 27 62 62 62 17 17 19
35 2 2 6 2 2 6 2 2 6 15 15 17 70 70 70 27 27 27
97 0 0 0 5 5 5 59 59 59 27 27 27 126 107 64 187 136 12
99 27 27 27 104 96 81 12 12 14 70 70 70 16 16 16 0 0 0
124 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 27 27 27
141 221 205 205 192 191 189 29 29 31 27 27 27 9 9 12 2 2 6
148 251 251 251 228 210 210 152 149 142 5 5 8 27 27 27 4 4 7
170 2 2 6 2 2 6 46 46 47 27 27 27 0 0 0 0 0 0
234 27 27 27 2 2 2 0 0 0 0 0 0
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac3_mac.h26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
48 #define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
65 #define MT_RXD2_NORMAL_FRAG BIT(27)
82 #define MT_RXD3_NORMAL_UDP_TCP_SUM BIT(27)
121 #define MT_CRXV_HE_LTF_SIZE GENMASK(28, 27)
127 #define MT_CRXV_HE_MU_AID GENMASK(27, 17)
142 #define MT_CRXV_HE_RU3_L GENMASK(31, 27)
146 #define MT_CRXV_EHT_LTF_SIZE GENMASK(28, 27)
150 #define MT_CRXV_EHT_MU_AID GENMASK(27, 17)
162 #define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
364 #define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
365 #define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1)
366 #define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2)
367 #define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3)
368 #define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4)
369 #define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)
370 #define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6)
371 #define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7)
372 #define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8)
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
122 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
132 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
143 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
/linux/arch/arc/boot/dts/
H A Dabilis_tb101.dtsi167 interrupts = <27 2>;
180 interrupts = <27 2>;
193 interrupts = <27 2>;
206 interrupts = <27 2>;
219 interrupts = <27 2>;
232 interrupts = <27 2>;
245 interrupts = <27 2>;
258 interrupts = <27 2>;
271 interrupts = <27 2>;
284 interrupts = <27 2>;
[all …]
H A Dabilis_tb100.dtsi158 interrupts = <27 2>;
171 interrupts = <27 2>;
184 interrupts = <27 2>;
197 interrupts = <27 2>;
210 interrupts = <27 2>;
223 interrupts = <27 2>;
236 interrupts = <27 2>;
249 interrupts = <27 2>;
262 interrupts = <27 2>;
275 interrupts = <27 2>;
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h94 #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
118 #define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
184 #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
222 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
354 #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27)
437 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
725 #define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
766 #define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)
776 #define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16)
778 #define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16)
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
44 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
62 MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
81 MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
94 MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
96 MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
115 MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
120 MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
131 MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
142 MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
[all …]
/linux/net/wireless/tests/
H A Dfragmentation.c18 [27] = 27, in defragment_0()
48 [27] = 27, in defragment_1()
91 [27] = 27, in defragment_2()
140 [27] = 27, in defragment_at_end()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h26 #define INSTR_SUBCLIENT_SHIFT 27
201 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
223 #define CMD_3DSTATE_MESH_CONTROL ((0x3 << 29) | (0x3 << 27) | (0x0 << 24) | (0x77 << 16) | (0x3))
244 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
287 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
290 #define PIPE_CONTROL_FLUSH_L3 (1<<27)
403 ((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
406 ((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
409 ((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
411 ((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h40 #define av1_dec_mode AV1_DEC_REG(3, 27, 0x1f)
122 #define av1_transform_mode AV1_DEC_REG(11, 27, 0x7)
227 #define av1_filt_level_delta1_seg7 AV1_DEC_REG(27, 0, 0x7f)
228 #define av1_filt_level_delta2_seg7 AV1_DEC_REG(27, 7, 0x7f)
229 #define av1_filt_level_delta3_seg7 AV1_DEC_REG(27, 14, 0x7f)
230 #define av1_global_mv_seg7 AV1_DEC_REG(27, 21, 0x1)
231 #define av1_mf2_last_offset AV1_DEC_REG(27, 22, 0x1ff)
308 #define av1_qmlevel_y AV1_DEC_REG(47, 27, 0xf)
313 #define av1_qmlevel_u AV1_DEC_REG(48, 27, 0xf)
338 #define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3)
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h77 * DF4 DstFabricID [27:16]
85 #define DF4_DST_FABRIC_ID GENMASK(27, 16)
122 * DF2 DieIdShift [27:24]
129 #define DF2_DIE_ID_SHIFT GENMASK(27, 24)
166 * DF4 DramBaseAddr [27:0]
169 * DF4p5 DramBaseAddr [27:0]
172 #define DF4_BASE_ADDR GENMASK(27, 0)
207 * DF4 DramLimitAddr [27:0]
210 * DF4p5 DramLimitAddr [27:0]
213 #define DF4_DRAM_LIMIT_ADDR GENMASK(27, 0)
[all …]
/linux/arch/alpha/lib/
H A Dcallback_srm.S28 ldq $27,0($2) # DISPATCH procedure descriptor (VMS call std)
30 ldq $3,8($27) # call address
38 ldgp $29,0($27)
46 ldq $27,16($2) # VA of FIXUP procedure descriptor
47 ldq $3,8($27) # call address
61 ldgp $29,0($27); br $25,srm_dispatch; .word CODE, ARG_CNT; .end callback_##NAME
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h149 #define CHNL_IER_AXI_WR_ERR_U_EN BIT(27)
159 #define CHNL_STS_AXI_WR_ERR_U BIT(27)
189 #define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)
196 #define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)
203 #define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)
258 #define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)
265 #define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)
278 #define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)
285 #define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)
298 #define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)
[all …]
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_types.h144 (1 << 27),
257 eSetup_UUIE_destExtraCallInfo = (1 << 27),
303 eCallProceeding_UUIE_cryptoTokens = (1 << 27),
325 eConnect_UUIE_cryptoTokens = (1 << 27),
353 eAlerting_UUIE_cryptoTokens = (1 << 27),
396 eFacility_UUIE_destExtraCallInfo = (1 << 27),
429 eProgress_UUIE_fastStart = (1 << 27),
518 (1 << 27),
609 eH323_UU_PDU_nonStandardControl = (1 << 27),
633 eGatekeeperRequest_alternateEndpoints = (1 << 27),
[all …]

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