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/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h71 #define R1_CLKSEL_USB (4 << 25)
88 #define R2_CLKSEL_USB (2 << 25)
105 #define RB_CLKSEL_USB (1 << 25)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
121 den = 25; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
139 den = 25; in realtime_counter_init()
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
H A Dnxp,tja11xx.yaml54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
79 description: Enable 50MHz RMII reference clock output on REF_CLK pin.
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
286 interrupts = <25>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsophgo,sg2042-pll.yaml21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/linux/drivers/clk/spear/
H A Dspear1340_clock.c107 #define SPEAR1340_DMA_CLK_ENB 25
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
H A Dspear1310_clock.c109 #define SPEAR1310_DMA_CLK_ENB 25
200 #define SPEAR1310_CAN1_CLK_ENB 25
231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
237 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
[all …]
/linux/drivers/media/tuners/
H A Dqt1010.c77 { QT1010_RD, 0x23, 0xff }, /* 25 c read */ in qt1010_set_params()
102 #define FREQ1 32000000 /* 32 MHz */ in qt1010_set_params()
103 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ in qt1010_set_params()
117 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ in qt1010_set_params()
118 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ in qt1010_set_params()
119 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ in qt1010_set_params()
125 /* 07 - set frequency: 32 MHz scale */ in qt1010_set_params()
128 /* 09 - changes every 8/24 MHz */ in qt1010_set_params()
132 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
[all …]
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux/drivers/clk/mvebu/
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
169 { "tdm", NULL, 25 },
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
115 return 25 * 1000 * 1000; in armada_39x_refclk_ratio()
/linux/drivers/clk/versatile/
H A Dclk-icst.c108 * 33 or 25 MHz respectively. in vco_get()
263 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
268 /* Slam to closest 0.25 MHz */ in icst_round_rate()
274 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
275 * select 25 MHz in icst_round_rate()
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
459 /* Maximum 50 MHz, VDW = 192 */
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h338 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
341 823437500, /* 823.4375 MHz PLL */
346 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
349 783360000, /* 783.36 MHz */
354 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
357 796875000, /* 796.875 MHz */
362 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
365 816000000, /* 816 MHz */
370 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
373 830078125, /* 830.78125 MHz */
[all …]
/linux/drivers/clk/sophgo/
H A DKconfig9 The driver require a 25MHz Oscillator to function generate clock.
19 frequency of 25 MHz as input, which are used for Main/Fixed
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
362 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
383 sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op); in sja1105_cfg_pad_mii_packing()
485 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
486 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
487 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
488 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
495 sja1105_packing(buf, &cmd->rxc_delay, 25, 21, size, op); in sja1110_cfg_pad_mii_id_packing()
601 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
604 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/mvm/tests/
H A Dlinks.c133 { .desc = "HB, 80 MHz, no channel load factor, punctured percentage 0",
142 { .desc = "HB, 160 MHz, no channel load factor, punctured percentage 25",
151 { .desc = "UHB, 320 MHz, no channel load factor, punctured percentage 12.5 (2/16)",
160 { .desc = "HB, 160 MHz, channel load 20, channel load by us 10, punctured percentage 25",
281 .desc = "RSSI: LB, 20 MHz, low",
289 .desc = "RSSI: UHB, 20 MHz, high",
298 .desc = "RSSI: UHB, 40 MHz, low",
307 .desc = "RSSI: UHB, 40 MHz, high",
316 .desc = "RSSI: UHB, 80 MHz, low",
325 .desc = "RSSI: UHB, 80 MHz, high",
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/linux/drivers/ssb/
H A Dmain.c858 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
859 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
860 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
861 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
865 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
871 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
878 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
879 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
894 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
895 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */

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