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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
[all …]
H A Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
H A Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
49 /* The codec chrystal operates at 24.576 MHz */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsophgo,sg2042-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
25 clock-names:
[all …]
H A Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
[all …]
H A Didt,versaclock5.txt9 - compatible: shall be one of
16 - reg: i2c device address, shall be 0x68 or 0x6a.
17 - #clock-cells: from common clock binding; shall be set to 1.
18 - clocks: from common clock binding; list of parent clock handles,
19 - 5p49v5923 and
23 - 5p49v5933 and
24 - 5p49v5935: (optional) property not present (internal
27 - clock-names: from common clock binding; clock input names, can be
28 - 5p49v5923 and
31 - 5p49v5933 and
[all …]
H A Dsilabs,si5351.txt5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
[all …]
H A Dallwinner,sun7i-a20-gmac-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
18 const: allwinner,sun7i-a20-gmac-clk
26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
[all …]
H A Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
21 - 5P49V5933:
22 0 -- OUT0_SEL_I2CB
23 1 -- OUT1
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * kitchen-sinked this device, not us. :)
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
52 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl
81 { -1, 0 }
119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
141 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
15 #include "qca-vendor.h"
28 * sub-type. */ in ieee802_11_parse_vendor_specific()
35 return -1; in ieee802_11_parse_vendor_specific()
41 /* Microsoft/Wi-Fi information elements are further typed and in ieee802_11_parse_vendor_specific()
47 elems->wpa_ie = pos; in ieee802_11_parse_vendor_specific()
48 elems->wpa_ie_len = elen; in ieee802_11_parse_vendor_specific()
57 return -1; in ieee802_11_parse_vendor_specific()
68 elems->wmm = pos; in ieee802_11_parse_vendor_specific()
69 elems->wmm_len = elen; in ieee802_11_parse_vendor_specific()
[all …]
H A Dhw_features_common.c3 * Copyright (c) 2002-2013, Jouni Malinen <j@w1.fi>
30 for (i = 0; i < mode->num_channels; i++) { in hw_get_channel_chan()
31 struct hostapd_channel_data *ch = &mode->channels[i]; in hw_get_channel_chan()
32 if (ch->chan == chan) { in hw_get_channel_chan()
34 *freq = ch->freq; in hw_get_channel_chan()
48 for (i = 0; i < mode->num_channels; i++) { in hw_mode_get_channel()
49 struct hostapd_channel_data *ch = &mode->channels[i]; in hw_mode_get_channel()
51 if (ch->freq == freq) { in hw_mode_get_channel()
53 *chan = ch->chan; in hw_mode_get_channel()
78 if (curr_mode->mode != mode) in hw_get_channel_freq()
[all …]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
48 * systems which are little-endian and do not do strange things with structure
49 * padding. (Big-endian host systems will require some byte-swapping.)
51 * -----
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
56 * -----
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
73 * - NNNN is an index of some form. Some item types are per-port, some
[all …]
/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_ht.c3 * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008, Intel Corporation
29 if (!hapd->iconf->ieee80211n || !hapd->iface->current_mode || in hostapd_eid_ht_capabilities()
30 hapd->conf->disable_11n || is_6ghz_op_class(hapd->iconf->op_class)) in hostapd_eid_ht_capabilities()
38 cap->ht_capabilities_info = host_to_le16(hapd->iconf->ht_capab); in hostapd_eid_ht_capabilities()
39 cap->a_mpdu_params = hapd->iface->current_mode->a_mpdu_params; in hostapd_eid_ht_capabilities()
40 os_memcpy(cap->supported_mcs_set, hapd->iface->current_mode->mcs_set, in hostapd_eid_ht_capabilities()
49 if (hapd->iconf->obss_interval) { in hostapd_eid_ht_capabilities()
57 scan_params->width_trigger_scan_interval = in hostapd_eid_ht_capabilities()
58 host_to_le16(hapd->iconf->obss_interval); in hostapd_eid_ht_capabilities()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation
14 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
16 * bandwidths <= 80MHz
18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
38 * enum iwl_tlc_mng_cfg_cw - channel width options
39 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
42 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dksz.txt6 - compatible: For external switch chips, compatible string must be exactly one
8 - "microchip,ksz8765"
9 - "microchip,ksz8794"
10 - "microchip,ksz8795"
11 - "microchip,ksz9477"
12 - "microchip,ksz9897"
13 - "microchip,ksz9896"
14 - "microchip,ksz9567"
15 - "microchip,ksz8565"
16 - "microchip,ksz9893"
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Ddove-cubox.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-1 {
32 compatible = "regulator-fixed";
33 regulator-name = "USB Power";
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
38 RX_ATTENTION_FLAGS_DIRECTED = BIT(25),
55 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
56 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
83 * Set if packet is not a non-QoS data frame. Only set when
107 * Set if packet is U-APSD trigger. Key table will have bits
108 * per TID to indicate U-APSD trigger.
178 * Indicates that the MPDU was pre-maturely terminated
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
101 #define PLLA_IDDQ_BIT 25
113 /* Post divider <-> register value mapping. */
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
306 /* PLLC: 510 MHz Clock source for camera use */
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
39 #define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)
49 (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain, in ar9280WriteRegs()
54 * Take the MHz channel value and set the Channel value
62 * (freq_ref = 40MHz)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
68 * For 5GHz channels which are 5MHz spaced,
70 * (freq_ref = 40MHz)
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
100 /* clock control registers (non-PMU devices) */
114 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sl-warp.dts4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 /dts-v1/;
50 #include <dt-bindings/gpio/gpio.h>
55 compatible = "revotics,imx6sl-warp", "fsl,imx6sl";
63 compatible = "mmc-pwrseq-simple";
64 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
66 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_uart1>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
42 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* Perform PHY chip noise-floor calculation */
45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */
46 #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */
47 #define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */
54 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001F /* Mask for kcos_theta-1 for q correction …
67 #define AR_PHY_PAPD_PROBE_GAINF_S 25
[all …]

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