Lines Matching +full:25 +full:- +full:mhz

1 /*-
2  * SPDX-License-Identifier: ISC
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2006 Atheros Communications, Inc.
42 #define	AR_PHY_AGC_CONTROL_NF	0x00000002	/* Perform PHY chip noise-floor calculation */
45 #define	AR_PHY_PLL_CTL_44	0x19	/* 44 MHz for 11b channels and FPGA */
46 #define	AR_PHY_PLL_CTL_40	0x18	/* 40 MHz */
47 #define	AR_PHY_PLL_CTL_20	0x13	/* 20 MHz half rate 11a for emulation */
54 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M	0x0000001F	/* Mask for kcos_theta-1 for q correction …
67 #define	AR_PHY_PAPD_PROBE_GAINF_S	25
82 #define	AR_PHY_IQCAL_RES_PWR_MEAS_I	0x9c10	/*PHY IQ calibration results - power measurement for I */
83 #define	AR_PHY_IQCAL_RES_PWR_MEAS_Q	0x9c14	/*PHY IQ calibration results - power measurement for Q */
84 #define	AR_PHY_IQCAL_RES_IQ_CORR_MEAS	0x9c18	/*PHY IQ calibration results - IQ correlation measurem…