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/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
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/linux/include/soc/tegra/
H A Dbpmp-abi.h44 * @brief Messages sent to/from BPMP via IPC
103 * @brief Header for an MRQ message
110 /** @brief MRQ number of the request */
114 * @brief 32bit word containing a number of fields as follows:
168 …* | MRQ_THERMAL | CMD_THERMAL_SET_TRIP | 20 …
207 …* | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_SET | 20 …
253 * @brief Header for an MRQ response
261 /** @brief Error code for the MRQ request itself */
265 * @brief 32bit word containing a number of fields as follows:
317 #define MRQ_RESET 20U
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/linux/Documentation/arch/arm/
H A Dmarvell.rst44 …- Product Brief : https://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-proc…
47 …- Product Brief : https://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-proc…
50 …- Product Brief : https://web.archive.org/web/20130730072715/http://www.marvell.com/embedded-proc…
55 …- Product Brief : https://web.archive.org/web/20131113121446/http://www.marvell.com/embedded-proc…
61 …- Product Brief : https://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-proc…
66 …- Product Brief : https://web.archive.org/web/20130730091058/http://www.marvell.com/embedded-proc…
69 …- Product Brief : https://web.archive.org/web/20120131133709/http://www.marvell.com/embedded-proc…
76 …- Product Brief : https://web.archive.org/web/20120616201639/http://www.marvell.com/embedded-proc…
92 …- Product Brief : https://web.archive.org/web/20120616194711/http://www.marvell.com/embedded-proc…
97 …- Product Brief : https://web.archive.org/web/20140801121623/http://www.marvell.com/embedded-proc…
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/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_driver.h50 * \brief Determine if I2C address 'addr' is a 10 bits address or not.
65 * \brief Initialize I2C communication module.
74 * \brief Terminate I2C communication module.
88 * \brief Read and/or write count bytes from I2C bus, store them in data[].
119 * \brief Returns a human readable error.
128 * \brief I2C specific error codes, platform dependent.
251 * \brief Enable I2C single or I2C multimaster mode on host.
266 * \brief Defines maximum chunksize of an i2c write action by host.
286 * \brief Defines maximum chunksize of an i2c read action by host.
307 * \brief Generic UNKNOWN value for DRX enumerated types.
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H A Ddrxj.c78 * \brief Maximum u32 value.
214 * \brief Default I2C address of a demodulator instance.
220 * \brief Default device identifier of a demodultor instance.
226 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
232 * \brief HI timing delay for I2C timing (in nano seconds)
240 * \brief HI timing delay for I2C timing (in nano seconds)
247 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
253 * \brief bit rate and segment rate constants used for SER and BER.
265 * \brief Min supported symbolrates.
272 * \brief Max supported symbolrates.
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/linux/sound/pci/ctxfi/
H A Dcthardware.c7 * @Brief
50 case 0x0005: /* 20k1 device */ in destroy_hw_obj()
53 case 0x000B: /* 20k2 device */ in destroy_hw_obj()
H A Dcthardware.h7 * @Brief
28 /* 20k1 models */
35 /* 20k2 models */
/linux/drivers/gpu/drm/msm/registers/display/
H A Dmdp4.xml10 <brief>pipe names, index into PIPE[]</brief>
65 <brief>appears to map pipe to mixer stage</brief>
76 <bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/>
311 <brief>8bit characters per pixel minus 1</brief>
317 <bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/>
/linux/arch/m68k/math-emu/
H A Dfp_decode.h133 | decode the 8bit displacement from the brief extension word
139 | decode the index of the brief/full extension word
188 | get the extension word and test for brief or full extension type
198 btst #20,%d2
/linux/include/dt-bindings/reset/
H A Dtegra186-reset.h30 #define TEGRA186_RESET_I2C2 20
202 /** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_IS…
H A Dtegra234-reset.h10 * @brief Identifiers for Resets controllable by firmware
32 #define TEGRA234_RESET_HDA 20U
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-ixdpg425.dts47 * CHECKME: the product brief says 16MB in a flash
100 queue-txready = <&qmgr 20>;
/linux/Documentation/RCU/
H A DNMI-RCU.rst14 brief explanation::
94 This works because (as of v4.20) synchronize_rcu() blocks until all
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Dadreno_common.xml60 <value name="FACTOR_SRC1_COLOR" value="20"/>
113 <brief>Registers in common between a2xx and a3xx</brief>
120 <bitfield name="POLL_EN" pos="20" type="boolean"/>
139 <bitfield name="MEQ_END" low="16" high="20" type="uint"/>
231 <bitfield pos="20" name="RCIU_ME_BUSY"/>
/linux/Documentation/networking/
H A Dregulatory.rst7 This document gives a brief review over how the Linux wireless
172 REG_RULE(2412-10, 2484+10, 40, 6, 20, 0),
174 REG_RULE(5170-10, 5240+10, 40, 6, 20,
177 REG_RULE(5260-10, 5320+10, 40, 6, 20,
/linux/drivers/hid/
H A Dhid-roccat-kone.h40 struct kone_keystroke keystrokes[20];
126 uint16_t checksum; /* \brief holds checksum of struct */
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1xxx_dbdma.h3 * BRIEF MODULE DESCRIPTION
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
149 #define AU1550_DSCR_CMD0_PSC3_TX 20
178 #define AU1200_DSCR_CMD0_CIM_RXC 20
206 #define AU1300_DSCR_CMD0_PSC3_TX 20
226 #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
H A Dau1000_dma.h2 * BRIEF MODULE DESCRIPTION
44 #define DMA_DAH_MASK (0x0f << 20)
H A Dau1xxx_psc.h3 * BRIEF MODULE DESCRIPTION
460 #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
H A Dau1000.h3 * BRIEF MODULE DESCRIPTION
260 #define MEM_SDMODE_BS (1 << 20)
270 #define MEM_SDMODE_BS_2Bank (0 << 20)
271 #define MEM_SDMODE_BS_4Bank (1 << 20)
290 #define MEM_SDADDR_E (1 << 20)
351 # define SYS_CNTRL_T1S (1 << 20)
419 # define SYS_PF_PSC3_MASK (7 << 20)
422 # define SYS_PF_PSC3_I2S (1 << 20)
423 # define SYS_PF_PSC3_SMBUS (3 << 20)
424 # define SYS_PF_PSC3_GPIO (7 << 20)
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/linux/Documentation/admin-guide/mm/
H A Dksm.rst90 e.g. ``echo 20 > /sys/kernel/mm/ksm/sleep_millisecs``
92 Default: 20 (chosen for demonstration purposes)
238 save each scanned page's brief rmap information. Some of these pages may
/linux/drivers/net/wireless/ath/ath11k/
H A Ddp.h235 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
242 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
244 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
367 * |31 24|23 20|19|18 16|15|14 8|7 0|
481 * b'20:31 - reserved: reserved for future use
714 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
768 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
804 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
1248 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20)
1273 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20)
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/linux/drivers/video/fbdev/
H A Dau1200fb.h2 * BRIEF MODULE DESCRIPTION
223 #define LCD_CLKCONTROL_DELAY (3<<20)
/linux/Documentation/arch/s390/
H A D3270.rst66 In brief, these are the steps:
261 command stack (default depth 20) and displayed in the input area. You
/linux/drivers/media/dvb-frontends/
H A Ddrxk_hard.c447 #define DRXK_MAX_RETRIES_POWERUP 20
3085 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); in init_agc()
3406 * \brief Activate DVBT specific presets
3446 * \brief Initialize channelswitch-independent settings for DVBT.
3658 * \brief start dvbt demodulating for channel.
3694 * \brief Set up dvbt demodulator for channel.
4031 * \brief Retrieve lock status .
4131 * \brief Setup of the QAM Measurement intervals for signal quality
4306 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in set_qam16()
4315 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in set_qam16()
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