1*9952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d5586560SJoseph Lo /* 3d5586560SJoseph Lo * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 4d5586560SJoseph Lo */ 5d5586560SJoseph Lo 6d5586560SJoseph Lo #ifndef _ABI_MACH_T186_RESET_T186_H_ 7d5586560SJoseph Lo #define _ABI_MACH_T186_RESET_T186_H_ 8d5586560SJoseph Lo 9d5586560SJoseph Lo 10d5586560SJoseph Lo #define TEGRA186_RESET_ACTMON 0 11d5586560SJoseph Lo #define TEGRA186_RESET_AFI 1 12d5586560SJoseph Lo #define TEGRA186_RESET_CEC 2 13d5586560SJoseph Lo #define TEGRA186_RESET_CSITE 3 14d5586560SJoseph Lo #define TEGRA186_RESET_DP2 4 15d5586560SJoseph Lo #define TEGRA186_RESET_DPAUX 5 16d5586560SJoseph Lo #define TEGRA186_RESET_DSI 6 17d5586560SJoseph Lo #define TEGRA186_RESET_DSIB 7 18d5586560SJoseph Lo #define TEGRA186_RESET_DTV 8 19d5586560SJoseph Lo #define TEGRA186_RESET_DVFS 9 20d5586560SJoseph Lo #define TEGRA186_RESET_ENTROPY 10 21d5586560SJoseph Lo #define TEGRA186_RESET_EXTPERIPH1 11 22d5586560SJoseph Lo #define TEGRA186_RESET_EXTPERIPH2 12 23d5586560SJoseph Lo #define TEGRA186_RESET_EXTPERIPH3 13 24d5586560SJoseph Lo #define TEGRA186_RESET_GPU 14 25d5586560SJoseph Lo #define TEGRA186_RESET_HDA 15 26d5586560SJoseph Lo #define TEGRA186_RESET_HDA2CODEC_2X 16 27d5586560SJoseph Lo #define TEGRA186_RESET_HDA2HDMICODEC 17 28d5586560SJoseph Lo #define TEGRA186_RESET_HOST1X 18 29d5586560SJoseph Lo #define TEGRA186_RESET_I2C1 19 30d5586560SJoseph Lo #define TEGRA186_RESET_I2C2 20 31d5586560SJoseph Lo #define TEGRA186_RESET_I2C3 21 32d5586560SJoseph Lo #define TEGRA186_RESET_I2C4 22 33d5586560SJoseph Lo #define TEGRA186_RESET_I2C5 23 34d5586560SJoseph Lo #define TEGRA186_RESET_I2C6 24 35d5586560SJoseph Lo #define TEGRA186_RESET_ISP 25 36d5586560SJoseph Lo #define TEGRA186_RESET_KFUSE 26 37d5586560SJoseph Lo #define TEGRA186_RESET_LA 27 38d5586560SJoseph Lo #define TEGRA186_RESET_MIPI_CAL 28 39d5586560SJoseph Lo #define TEGRA186_RESET_PCIE 29 40d5586560SJoseph Lo #define TEGRA186_RESET_PCIEXCLK 30 41d5586560SJoseph Lo #define TEGRA186_RESET_SATA 31 42d5586560SJoseph Lo #define TEGRA186_RESET_SATACOLD 32 43d5586560SJoseph Lo #define TEGRA186_RESET_SDMMC1 33 44d5586560SJoseph Lo #define TEGRA186_RESET_SDMMC2 34 45d5586560SJoseph Lo #define TEGRA186_RESET_SDMMC3 35 46d5586560SJoseph Lo #define TEGRA186_RESET_SDMMC4 36 47d5586560SJoseph Lo #define TEGRA186_RESET_SE 37 48d5586560SJoseph Lo #define TEGRA186_RESET_SOC_THERM 38 49d5586560SJoseph Lo #define TEGRA186_RESET_SOR0 39 50d5586560SJoseph Lo #define TEGRA186_RESET_SPI1 40 51d5586560SJoseph Lo #define TEGRA186_RESET_SPI2 41 52d5586560SJoseph Lo #define TEGRA186_RESET_SPI3 42 53d5586560SJoseph Lo #define TEGRA186_RESET_SPI4 43 54d5586560SJoseph Lo #define TEGRA186_RESET_TMR 44 55d5586560SJoseph Lo #define TEGRA186_RESET_TRIG_SYS 45 56d5586560SJoseph Lo #define TEGRA186_RESET_TSEC 46 57d5586560SJoseph Lo #define TEGRA186_RESET_UARTA 47 58d5586560SJoseph Lo #define TEGRA186_RESET_UARTB 48 59d5586560SJoseph Lo #define TEGRA186_RESET_UARTC 49 60d5586560SJoseph Lo #define TEGRA186_RESET_UARTD 50 61d5586560SJoseph Lo #define TEGRA186_RESET_VI 51 62d5586560SJoseph Lo #define TEGRA186_RESET_VIC 52 63d5586560SJoseph Lo #define TEGRA186_RESET_XUSB_DEV 53 64d5586560SJoseph Lo #define TEGRA186_RESET_XUSB_HOST 54 65d5586560SJoseph Lo #define TEGRA186_RESET_XUSB_PADCTL 55 66d5586560SJoseph Lo #define TEGRA186_RESET_XUSB_SS 56 67d5586560SJoseph Lo #define TEGRA186_RESET_AON_APB 57 68d5586560SJoseph Lo #define TEGRA186_RESET_AXI_CBB 58 69d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_APB 59 70d5586560SJoseph Lo #define TEGRA186_RESET_CAN1 60 71d5586560SJoseph Lo #define TEGRA186_RESET_CAN2 61 72d5586560SJoseph Lo #define TEGRA186_RESET_DMIC5 62 73d5586560SJoseph Lo #define TEGRA186_RESET_DSIC 63 74d5586560SJoseph Lo #define TEGRA186_RESET_DSID 64 75d5586560SJoseph Lo #define TEGRA186_RESET_EMC_EMC 65 76d5586560SJoseph Lo #define TEGRA186_RESET_EMC_MEM 66 77d5586560SJoseph Lo #define TEGRA186_RESET_EMCSB_EMC 67 78d5586560SJoseph Lo #define TEGRA186_RESET_EMCSB_MEM 68 79d5586560SJoseph Lo #define TEGRA186_RESET_EQOS 69 80d5586560SJoseph Lo #define TEGRA186_RESET_GPCDMA 70 81d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL0 71 82d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL1 72 83d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL2 73 84d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL3 74 85d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL4 75 86d5586560SJoseph Lo #define TEGRA186_RESET_GPIO_CTL5 76 87d5586560SJoseph Lo #define TEGRA186_RESET_I2C10 77 88d5586560SJoseph Lo #define TEGRA186_RESET_I2C12 78 89d5586560SJoseph Lo #define TEGRA186_RESET_I2C13 79 90d5586560SJoseph Lo #define TEGRA186_RESET_I2C14 80 91d5586560SJoseph Lo #define TEGRA186_RESET_I2C7 81 92d5586560SJoseph Lo #define TEGRA186_RESET_I2C8 82 93d5586560SJoseph Lo #define TEGRA186_RESET_I2C9 83 94d5586560SJoseph Lo #define TEGRA186_RESET_JTAG2AXI 84 95d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_IOBIST 85 96d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_L0_RX 86 97d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_L0_TX 87 98d5586560SJoseph Lo #define TEGRA186_RESET_NVCSI 88 99d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 100d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 101d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 102d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_MISC 92 103d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 104d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 105d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 106d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 107d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 108d5586560SJoseph Lo #define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 109d5586560SJoseph Lo #define TEGRA186_RESET_PWM1 99 110d5586560SJoseph Lo #define TEGRA186_RESET_PWM2 100 111d5586560SJoseph Lo #define TEGRA186_RESET_PWM3 101 112d5586560SJoseph Lo #define TEGRA186_RESET_PWM4 102 113d5586560SJoseph Lo #define TEGRA186_RESET_PWM5 103 114d5586560SJoseph Lo #define TEGRA186_RESET_PWM6 104 115d5586560SJoseph Lo #define TEGRA186_RESET_PWM7 105 116d5586560SJoseph Lo #define TEGRA186_RESET_PWM8 106 117d5586560SJoseph Lo #define TEGRA186_RESET_SCE_APB 107 118d5586560SJoseph Lo #define TEGRA186_RESET_SOR1 108 119d5586560SJoseph Lo #define TEGRA186_RESET_TACH 109 120d5586560SJoseph Lo #define TEGRA186_RESET_TSC 110 121d5586560SJoseph Lo #define TEGRA186_RESET_UARTF 111 122d5586560SJoseph Lo #define TEGRA186_RESET_UARTG 112 123d5586560SJoseph Lo #define TEGRA186_RESET_UFSHC 113 124d5586560SJoseph Lo #define TEGRA186_RESET_UFSHC_AXI_M 114 125d5586560SJoseph Lo #define TEGRA186_RESET_UPHY 115 126d5586560SJoseph Lo #define TEGRA186_RESET_ADSP 116 127d5586560SJoseph Lo #define TEGRA186_RESET_ADSPDBG 117 128d5586560SJoseph Lo #define TEGRA186_RESET_ADSPINTF 118 129d5586560SJoseph Lo #define TEGRA186_RESET_ADSPNEON 119 130d5586560SJoseph Lo #define TEGRA186_RESET_ADSPPERIPH 120 131d5586560SJoseph Lo #define TEGRA186_RESET_ADSPSCU 121 132d5586560SJoseph Lo #define TEGRA186_RESET_ADSPWDT 122 133d5586560SJoseph Lo #define TEGRA186_RESET_APE 123 134d5586560SJoseph Lo #define TEGRA186_RESET_DPAUX1 124 135d5586560SJoseph Lo #define TEGRA186_RESET_NVDEC 125 136d5586560SJoseph Lo #define TEGRA186_RESET_NVENC 126 137d5586560SJoseph Lo #define TEGRA186_RESET_NVJPG 127 138d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY 128 139d5586560SJoseph Lo #define TEGRA186_RESET_QSPI 129 140d5586560SJoseph Lo #define TEGRA186_RESET_TSECB 130 141d5586560SJoseph Lo #define TEGRA186_RESET_VI_I2C 131 142d5586560SJoseph Lo #define TEGRA186_RESET_UARTE 132 143d5586560SJoseph Lo #define TEGRA186_RESET_TOP_GTE 133 144d5586560SJoseph Lo #define TEGRA186_RESET_SHSP 134 145d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L5 135 146d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L4 136 147d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L3 137 148d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L2 138 149d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L1 139 150d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_L0 140 151d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 152d5586560SJoseph Lo #define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 153d5586560SJoseph Lo #define TEGRA186_RESET_TSCTNVI 143 154d5586560SJoseph Lo #define TEGRA186_RESET_EXTPERIPH4 144 155d5586560SJoseph Lo #define TEGRA186_RESET_DSIPADCTL 145 156d5586560SJoseph Lo #define TEGRA186_RESET_AUD_MCLK 146 157d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_CLK_CTL 147 158d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_L1_RX 148 159d5586560SJoseph Lo #define TEGRA186_RESET_MPHY_L1_TX 149 160d5586560SJoseph Lo #define TEGRA186_RESET_UFSHC_LP 150 161d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_NIC 151 162d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_NSYSPORESET 152 163d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_NRESET 153 164d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_DBGRESETN 154 165d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_PRESETDBGN 155 166d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_PM 156 167d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_CVC 157 168d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_DMA 158 169d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_HSP 159 170d5586560SJoseph Lo #define TEGRA186_RESET_TSCTNBPMP 160 171d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_TKE 161 172d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_GTE 162 173d5586560SJoseph Lo #define TEGRA186_RESET_BPMP_PM_ACTMON 163 174d5586560SJoseph Lo #define TEGRA186_RESET_AON_NIC 164 175d5586560SJoseph Lo #define TEGRA186_RESET_AON_NSYSPORESET 165 176d5586560SJoseph Lo #define TEGRA186_RESET_AON_NRESET 166 177d5586560SJoseph Lo #define TEGRA186_RESET_AON_DBGRESETN 167 178d5586560SJoseph Lo #define TEGRA186_RESET_AON_PRESETDBGN 168 179d5586560SJoseph Lo #define TEGRA186_RESET_AON_ACTMON 169 180d5586560SJoseph Lo #define TEGRA186_RESET_AOPM 170 181d5586560SJoseph Lo #define TEGRA186_RESET_AOVC 171 182d5586560SJoseph Lo #define TEGRA186_RESET_AON_DMA 172 183d5586560SJoseph Lo #define TEGRA186_RESET_AON_GPIO 173 184d5586560SJoseph Lo #define TEGRA186_RESET_AON_HSP 174 185d5586560SJoseph Lo #define TEGRA186_RESET_TSCTNAON 175 186d5586560SJoseph Lo #define TEGRA186_RESET_AON_TKE 176 187d5586560SJoseph Lo #define TEGRA186_RESET_AON_GTE 177 188d5586560SJoseph Lo #define TEGRA186_RESET_SCE_NIC 178 189d5586560SJoseph Lo #define TEGRA186_RESET_SCE_NSYSPORESET 179 190d5586560SJoseph Lo #define TEGRA186_RESET_SCE_NRESET 180 191d5586560SJoseph Lo #define TEGRA186_RESET_SCE_DBGRESETN 181 192d5586560SJoseph Lo #define TEGRA186_RESET_SCE_PRESETDBGN 182 193d5586560SJoseph Lo #define TEGRA186_RESET_SCE_ACTMON 183 194d5586560SJoseph Lo #define TEGRA186_RESET_SCE_PM 184 195d5586560SJoseph Lo #define TEGRA186_RESET_SCE_DMA 185 196d5586560SJoseph Lo #define TEGRA186_RESET_SCE_HSP 186 197d5586560SJoseph Lo #define TEGRA186_RESET_TSCTNSCE 187 198d5586560SJoseph Lo #define TEGRA186_RESET_SCE_TKE 188 199d5586560SJoseph Lo #define TEGRA186_RESET_SCE_GTE 189 200d5586560SJoseph Lo #define TEGRA186_RESET_SCE_CFG 190 201d5586560SJoseph Lo #define TEGRA186_RESET_ADSP_ALL 191 202d5586560SJoseph Lo /** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ 203d5586560SJoseph Lo #define TEGRA186_RESET_UFSHC_LP_SEQ 192 204d5586560SJoseph Lo #define TEGRA186_RESET_SIZE 193 205d5586560SJoseph Lo 206d5586560SJoseph Lo #endif 207