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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchFixupKinds.h1 //===- LoongArchFixupKinds.h - LoongArch Specific Fixup Entries -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne.
28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez.
30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl.
32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
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H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
59 #define MT_TXD1_TID GENMASK(22, 20)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
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H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVFixupKinds.h1 //===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries ------
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/freebsd/contrib/llvm-project/libcxx/include/
H A Dbit1 // -*- C++ -*-
2 //===----------------------------------------------------------------------===//
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===---------------------------------------------------------------------===//
14 bit synopsis
17 // [bit.cast], bit_cast
19 constexpr To bit_cast(const From& from) noexcept; // C++20
21 // [bit.byteswap], byteswap
25 // [bit.pow.two], integral powers of 2
27 constexpr bool has_single_bit(T x) noexcept; // C++20
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
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H A DRISCVInstrFormats.td1 //===-- RISCVInstrFormats.td - RISC-V Instruction Formats --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // description in the RISC-V User-Level ISA specification as closely as
14 // MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
18 // specification describes immediate encoding in terms of bit-slicing
20 // these instruction formats instead represents the bit sequence that will be
22 // a 21-bit value (where the LSB is always zero), we describe it as an imm20
25 //===----------------------------------------------------------------------===//
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/file/magic/Magdir/
H A Dcoff2 #------------------------------------------------------------------------------
12 # https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#coff-file-header-object-and-image
16 0 name display-coff-processor
20 >0 uleshort 0x0160 MIPS R3000 (big-endian)
25 >0 uleshort 0x0184 Alpha 32-bit
37 >0 uleshort 0x01f0 PowerPC 32-bit (little-endian)
38 >0 uleshort 0x01f1 PowerPC 32-bit with FPU (little-endian)
39 >0 uleshort 0x01f2 PowerPC 64-bit (big-endian)
43 >0 uleshort 0x0284 Alpha 64-bit
44 >0 uleshort 0x0290 PA-RISC
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H A Daudio2 #------------------------------------------------------------------------------
3 # $File: audio,v 1.133 2024/09/04 19:07:20 christos Exp $
12 >12 belong 1 8-bit ISDN mu-law,
14 >12 belong 2 8-bit linear PCM [REF-PCM],
16 >12 belong 3 16-bit linear PCM,
18 >12 belong 4 24-bit linear PCM,
20 >12 belong 5 32-bit linear PCM,
22 >12 belong 6 32-bit IEEE floating point,
24 >12 belong 7 64-bit IEEE floating point,
28 >12 belong 11 8-bit fixed point,
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H A Dfreebsd2 #------------------------------------------------------------------------------
6 # All new-style FreeBSD magic numbers are in host byte order (i.e.,
7 # little-endian on x86).
9 # XXX - this comes from the file "freebsd" in a recent FreeBSD version of
16 # Regardless of whether it's pure, demand-paged, or none of the
20 # the "has run-time loader information" bit is set, and is
21 # position-independent if the "is position-independent" bit
25 # an executable, and is dynamically-linked if the "has run-time
26 # loader information" bit is set.
30 # If it's neither pure nor demand-paged:
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_27.out25 20 2 16 3
34 be: 0 -1 000000000000000000000000000
35 is: 0 -1 000000000000000000000000000
67 20 0
76 be: 0 -1 000000000000000000000000000
77 is: 0 -1 000000000000000000000000000
84 be: 0 -1 000000000000000000000000000
85 is: 0 -1 000000000000000000000000000
88 be: 0 -1 000000000000000000000000000
89 is: 0 -1 000000000000000000000000000
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H A Dd_bitstring_32.out25 20 2 16 3
39 be: 0 -1 00000000000000000000000000000000
40 is: 0 -1 00000000000000000000000000000000
72 20 0
86 be: 0 -1 00000000000000000000000000000000
87 is: 0 -1 00000000000000000000000000000000
94 be: 0 -1 00000000000000000000000000000000
95 is: 0 -1 00000000000000000000000000000000
98 be: 0 -1 00000000000000000000000000000000
99 is: 0 -1 00000000000000000000000000000000
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/freebsd/share/man/man4/
H A Dahc.42 .\" SPDX-License-Identifier: BSD-3-Clause
39 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
66 .Tn SCSI-Select
74 For systems that store non-volatile settings in a system specific manner
80 many chip-down motherboard configurations.
90 .Bd -ragged -offset indent
91 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
93 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
94 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation
14 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
29 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
30 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
31 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
32 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
33 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
34 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6),
38 * enum iwl_tlc_mng_cfg_cw - channel width options
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
194 #define FRF_AB_PCIE_DEQ5_LBN 20
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
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/freebsd/contrib/bearssl/src/symcipher/
H A Dpoly1305_ctmulq.c52 * The "accumulator" word is nominally a 130-bit value. We split it into
53 * words of 44 bits, each held in a 64-bit variable.
64 * We want to reduce that value modulo p = 2^130-5, so W^3 = 20 mod p,
65 * and W^4 = 20*W mod p. Thus, if we define u1 = 20*r1 and u2 = 20*r2,
80 * bits of u1. Note that since r is clamped down to a 124-bit value, the
87 * e0 = c0 + 20*d2
95 * need to compute the additions (for the bx values) over 128-bit
96 * quantities; we can stick to 64-bit computations.
99 * Since the 128-bit result of a 64x64 multiplication is actually
100 * represented over two 64-bit registers, it is cheaper to arrange for
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/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_ht.c3 * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008, Intel Corporation
29 if (!hapd->iconf->ieee80211n || !hapd->iface->current_mode || in hostapd_eid_ht_capabilities()
30 hapd->conf->disable_11n || is_6ghz_op_class(hapd->iconf->op_class)) in hostapd_eid_ht_capabilities()
38 cap->ht_capabilities_info = host_to_le16(hapd->iconf->ht_capab); in hostapd_eid_ht_capabilities()
39 cap->a_mpdu_params = hapd->iface->current_mode->a_mpdu_params; in hostapd_eid_ht_capabilities()
40 os_memcpy(cap->supported_mcs_set, hapd->iface->current_mode->mcs_set, in hostapd_eid_ht_capabilities()
49 if (hapd->iconf->obss_interval) { in hostapd_eid_ht_capabilities()
57 scan_params->width_trigger_scan_interval = in hostapd_eid_ht_capabilities()
58 host_to_le16(hapd->iconf->obss_interval); in hostapd_eid_ht_capabilities()
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/freebsd/sys/contrib/dev/rtw88/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
18 #define BIT_RST_TRXDMA_INTF BIT(20)
19 #define BIT_RX_TAG_EN BIT(15)
23 #define BIT_DBI_RFLAG BIT(17)
24 #define BIT_DBI_WFLAG BIT(16)
31 #define BIT_MDIO_WFLAG_V1 BIT(5)
32 #define RTW_PCI_MDIO_PG_SZ BIT(5)
35 #define RTW_PCI_WR_RETRY_CNT 20
38 #define BIT_CLKREQ_SW_EN BIT(4)
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