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Searched +full:1 +full:_chan (Results 1 – 24 of 24) sorted by relevance

/linux/sound/pci/hda/
H A Dca0132_regs.h33 #define XRAM_XRAM_INST_OFFSET(_chan) \ argument
35 (_chan * XRAM_XRAM_CHAN_INCR))
41 #define YRAM_YRAM_INST_OFFSET(_chan) \ argument
43 (_chan * YRAM_YRAM_CHAN_INCR))
49 #define UC_UC_INST_OFFSET(_chan) \ argument
51 (_chan * UC_UC_CHAN_INCR))
57 #define AXRAM_AXRAM_INST_OFFSET(_chan) \ argument
59 (_chan * AXRAM_AXRAM_CHAN_INCR))
65 #define AYRAM_AYRAM_INST_OFFSET(_chan) \ argument
67 (_chan * AYRAM_AYRAM_CHAN_INCR))
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h39 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
48 * | register block for quad 0 | register block for quad 1 |
50 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
57 * * PHY port 5 is port 1 in quad 1
122 u8 init : 1;
123 u8 calibrating : 1;
124 u8 has_ready_bitmap : 1;
195 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
196 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
197 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
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/linux/drivers/iio/adc/
H A Dltc2497-core.c46 return 1; in ltc2497core_wait_conv()
99 *val2 = ddata->chip_info->resolution + 1; in ltc2497core_read_raw()
108 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
110 .indexed = 1, \
111 .channel = (_chan), \
112 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
118 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
120 .indexed = 1, \
121 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
122 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
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H A Dltc2309.c43 /* Order matches expected channel address, See datasheet Table 1. */
63 #define LTC2309_CHAN(_chan, _addr) { \ argument
65 .indexed = 1, \
67 .channel = _chan, \
72 #define LTC2309_DIFF_CHAN(_chan, _chan2, _addr) { \ argument
74 .differential = 1, \
75 .indexed = 1, \
77 .channel = _chan, \
85 LTC2309_CHAN(1, LTC2309_CH1),
92 LTC2309_DIFF_CHAN(0, 1, LTC2309_CH0_CH1),
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H A Dxilinx-xadc-core.c111 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
114 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
116 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
179 uint32_t cmd[1]; in xadc_zynq_write_adc_reg()
218 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0); in xadc_zynq_read_adc_reg()
229 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; in xadc_zynq_read_adc_reg()
251 ((alarm & 0x78) << 1) | in xadc_zynq_transform_alarm()
437 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07); in xadc_zynq_update_alarm()
525 events = (status & 0x000e) >> 1; in xadc_axi_interrupt_handler()
547 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | in xadc_axi_update_alarm()
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H A Dti-ads7924.c58 * Register address INC bit: when set to '1', the register address is
66 #define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0)
68 #define ADS7924_CFG_INTPOL_BIT 1
76 #define ADS7924_CFG_INTPOL_HIGH 1
80 #define ADS7924_CFG_INTTRIG_EDGE 1
122 #define ADS7924_V_CHAN(_chan, _addr) { \ argument
124 .indexed = 1, \
125 .channel = _chan, \
129 .datasheet_name = "AIN"#_chan, \
187 ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
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H A Dad7292.c45 #define AD7292_VOLTAGE_CHAN(_chan) \ argument
50 .indexed = 1, \
51 .channel = _chan, \
56 AD7292_VOLTAGE_CHAN(1),
69 .indexed = 1,
70 .differential = 1,
72 .channel2 = 1,
96 ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2); in ad7292_spi_reg_read()
110 st->d8[1] = sub_addr; in ad7292_spi_subreg_read()
139 st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM); in ad7292_single_conversion()
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H A Dad9467.c188 unsigned char tbuf[2], rbuf[1]; in ad9467_spi_read()
192 tbuf[1] = reg & 0xFF; in ad9467_spi_read()
208 st->buf[1] = reg & 0xFF; in ad9467_spi_write()
268 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5},
284 #define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \ argument
287 .indexed = 1, \
288 .channel = _chan, \
310 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 14, 's'),
319 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 16, 's'),
350 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
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/linux/drivers/dma/
H A Dfsl-edma-common.h13 #define EDMA_CR_EDBG BIT(1)
38 #define EDMA_TCD_CSR_INT_MAJOR BIT(1)
48 #define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
49 #define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
67 #define EDMA_V3_CH_CSR_EARQ BIT(1)
193 #define FSL_EDMA_DRV_MUX_SWAP BIT(1)
314 #define fsl_edma_get_tcd(_chan, _tcd, _field) \ argument
315 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
325 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ argument
326 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
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H A Dfsl-edma-main.c62 edma_writel_chreg(fsl_chan, 1, ch_int); in fsl_edma3_tx_handler()
178 struct dma_chan *chan, *_chan; in fsl_edma_xlate() local
188 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
192 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1])) in fsl_edma_xlate()
200 fsl_chan->srcid = dma_spec->args[1]; in fsl_edma_xlate()
221 struct dma_chan *chan, *_chan; in fsl_edma3_xlate() local
232 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
243 fsl_chan->priority = dma_spec->args[1]; in fsl_edma3_xlate()
391 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. in fsl_edma2_irq_init()
403 if (i == count - 1) { in fsl_edma2_irq_init()
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H A Dat_xdmac.c30 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
32 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
114 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
115 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
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H A Dfsl-edma-common.c188 int endian_diff[4] = {3, 1, -1, -3}; in fsl_edma_chan_mux()
216 val = ffs(addr_width) - 1; in fsl_edma_get_tcd_attr()
633 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd; in fsl_edma_prep_dma_cyclic()
734 for (j = burst; j > 1; j--) { in fsl_edma_prep_slave_sg()
740 /* Set burst size as 1 if there's no suitable one */ in fsl_edma_prep_slave_sg()
741 if (j == 1) in fsl_edma_prep_slave_sg()
745 if (i < sg_len - 1) { in fsl_edma_prep_memcpy()
746 last_sg = fsl_desc->tcd[(i + 1)].ptcd; in fsl_edma_prep_memcpy()
770 fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1); in fsl_edma_xfer_desc()
860 struct fsl_edma_chan *chan, *_chan; fsl_edma_cleanup_vchan() local
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H A Dmv_xor.c95 hw_desc->desc_command |= (1 << index); in mv_desc_set_src_addr()
170 return (state == 1) ? 1 : 0; in mv_chan_is_busy()
294 current_cleaned = 1; in mv_chan_slot_cleanup()
388 int new_hw_chain = 1; in mv_xor_tx_submit()
421 new_hw_chain = 1; in mv_xor_tx_submit()
524 size -= 1; in mv_xor_add_io_win()
534 i = ffs(~win_enable) - 1; in mv_xor_add_io_win()
546 win_enable |= (1 << i); in mv_xor_add_io_win()
549 writel(win_enable, base + WINDOW_BAR_ENABLE(1)); in mv_xor_add_io_win()
606 return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); in mv_xor_prep_dma_memcpy()
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/linux/drivers/input/touchscreen/
H A Dtsc2007_iio.c15 #define TSC2007_CHAN_IIO(_chan, _name, _type, _chan_info) \ argument
21 .indexed = 1, \
22 .channel = _chan, \
27 TSC2007_CHAN_IIO(1, "y", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
58 case 1: in tsc2007_read_raw()
/linux/drivers/iio/dac/
H A Dad5764.c75 #define AD5764_CHANNEL(_chan, _bits) { \ argument
77 .indexed = 1, \
78 .output = 1, \
79 .channel = (_chan), \
80 .address = (_chan), \
97 AD5764_CHANNEL(1, (_bits)), \
133 ret = spi_write(st->spi, &st->data[0].d8[1], 3); in ad5764_write()
146 .tx_buf = &st->data[0].d8[1], in ad5764_read()
148 .cs_change = 1, in ad5764_read()
150 .rx_buf = &st->data[1].d8[1], in ad5764_read()
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H A Dad5766.c21 #define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
86 "1",
101 * 0 - Normal operation, 1 - Power down
105 * 1: N0, 2: N1
108 * 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
153 .cs_change = 1, in __ad5766_spi_read()
155 .tx_buf = &st->data[1].d32, in __ad5766_spi_read()
163 st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT; in __ad5766_spi_read()
169 *val = st->data[2].w16[1]; in __ad5766_spi_read()
177 put_unaligned_be16(data, &st->data[0].b8[1]); in __ad5766_spi_write()
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H A Dltc2632.c118 if (val >= (1 << chan->scan_type.realbits) || val < 0) in ltc2632_write_raw()
138 !!(st->powerdown_cache_mask & (1 << chan->channel))); in ltc2632_read_dac_powerdown()
156 st->powerdown_cache_mask |= (1 << chan->channel); in ltc2632_write_dac_powerdown()
158 st->powerdown_cache_mask &= ~(1 << chan->channel); in ltc2632_write_dac_powerdown()
182 #define LTC2632_CHANNEL(_chan, _bits) { \
184 .indexed = 1, \ argument
185 .output = 1, \
186 .channel = (_chan), \
189 .address = (_chan), \
200 LTC2632_CHANNEL(1, _bit
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H A Dltc2688.c54 #define LTC2688_DITHER_RAW_MAX_VAL (BIT(14) - 1)
55 #define LTC2688_CH_CALIBBIAS_MAX_VAL (BIT(14) - 1)
59 #define LTC2688_CONFIG_EXT_REF BIT(1)
109 .cs_change = 1, in ltc2688_spi_read()
125 memcpy(val, &st->rx_data[1], val_size); in ltc2688_spi_read()
166 fs = ltc2688_span_helper[span][1] - ltc2688_span_helper[span][0]; in ltc2688_scale_get()
257 static const int ltc2688_raw_range[] = {0, 1, U16_MAX};
424 buf[sz - 1] = '\n'; in ltc2688_dither_freq_avail()
501 ltc2688_raw_range[1], in ltc2688_dac_input_read()
661 #define LTC2688_CHANNEL(_chan) { \ argument
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/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-pktdma.yaml78 minItems: 1
89 minItems: 1
100 minItems: 1
111 minItems: 1
189 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
190 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
/linux/drivers/comedi/drivers/
H A Ddas6402.c22 * [1] - IRQ (optional, needed for async command support)
43 #define DAS6402_STATUS_FHALF BIT(1)
51 #define DAS6402_STATUS_W_CLRXTR BIT(1)
60 #define DAS6402_CTRL_EXT_FALL_TRIG DAS6402_CTRL_TRIG(1)
69 #define DAS6402_TRIG_TGSEL BIT(1)
72 #define DAS6402_AO_RANGE(_chan, _range) ((_range) << ((_chan) ? 6 : 4)) argument
73 #define DAS6402_AO_RANGE_MASK(_chan) (3 << ((_chan) ? 6 : 4)) argument
77 #define DAS6402_MODE_FIFONEPTY DAS6402_MODE_RANGE(1)
85 #define DAS6402_MODE_DMA3 DAS6402_MODE_DMA(1)
190 comedi_buf_write_samples(s, &val, 1); in das6402_interrupt()
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/linux/drivers/regulator/
H A Dmax5970-regulator.c45 *val = (reg_data[0] << 2) | (reg_data[1] & 3); in max5970_read_adc()
366 #define MAX597X_SWITCH(_ID, _ereg, _chan, _supply) { \ argument
376 .enable_mask = CHXEN((_chan)), \
382 MAX597X_SWITCH(sw1, MAX5970_REG_CHXEN, 1, "vss2"),
422 *dev_mask |= 1 << i; in max597x_irq_handler()
426 *dev_mask |= 1 << i; in max597x_irq_handler()
440 *dev_mask |= 1 << i; in max597x_irq_handler()
444 *dev_mask |= 1 << i; in max597x_irq_handler()
458 *dev_mask |= 1 << i; in max597x_irq_handler()
473 *dev_mask |= 1 << i; in max597x_irq_handler()
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/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-fh.h126 * set to 1 - interrupt is sent to the driver
154 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
160 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
162 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
194 * "read" index has advanced past 1! See below).
205 * corresponding to the "read" index. For example, if "read" index becomes "1",
236 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
268 * typical value 0x10 (about 1/2 msec)
311 * 24: 1 = Channel 0 is idle
426 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
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/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c92 * - Even chunks originate CB equal to 1 in dw_edma_alloc_chunk()
212 return 1; in dw_edma_start_transfer()
388 * 1. Normal logic: in dw_edma_device_transfer()
418 if (xfer->xfer.sg.len < 1) in dw_edma_device_transfer()
421 if (!xfer->xfer.il->numf || xfer->xfer.il->frame_size < 1) in dw_edma_device_transfer()
746 chan->ll_max -= 1; in dw_edma_channel_setup()
752 if (dw->nr_irqs == 1) in dw_edma_channel_setup()
835 u32 wr_mask = 1; in dw_edma_irq_request()
836 u32 rd_mask = 1; in dw_edma_irq_request()
843 if (chip->nr_irqs < 1 || !chip->ops->irq_vector) in dw_edma_irq_request()
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_nix.c99 while (i + 1 < MAX_NIX_BLKS) { in rvu_get_next_nix_blkaddr()
101 return rvu->nix_blkaddr[i + 1]; in rvu_get_next_nix_blkaddr()
360 pfvf->rx_chan_cnt = 1; in nix_interface_init()
361 pfvf->tx_chan_cnt = 1; in nix_interface_init()
368 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; in nix_interface_init()
372 * send packets on lbk link 1 channels and NIX1 should send in nix_interface_init()
377 if (rvu->hw->lbk_links > 1) in nix_interface_init()
378 lbkid = vf & 0x1 ? 0 : 1; in nix_interface_init()
380 /* By default NIX0 is configured to send packet on lbk link 1 in nix_interface_init()
384 * link 1. in nix_interface_init()
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