Lines Matching +full:1 +full:_chan
13 #define EDMA_CR_EDBG BIT(1)
38 #define EDMA_TCD_CSR_INT_MAJOR BIT(1)
48 #define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
49 #define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
67 #define EDMA_V3_CH_CSR_EARQ BIT(1)
75 #define EDMA_V3_CH_ERR_SBE BIT(1)
208 #define FSL_EDMA_DRV_MUX_SWAP BIT(1)
332 #define fsl_edma_get_tcd(_chan, _tcd, _field) \ argument
333 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
343 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ argument
344 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
355 #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \ argument
357 if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64) \