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/linux/drivers/net/fddi/skfp/
H A Dsmtdef.c46 #define DEFAULT_T_NON_OP TTS(1)
54 #define DEFAULT_TEST_DONE TTS(1)
55 #define DEFAULT_CHECK_POLL TTS(1)
61 #define DEFAULT_LCT_SHORT 1
69 static int set_min_max(int maxflag, u_long mib, u_long limit, u_long *oper);
89 smt->build_ring_map = 1 ; in smt_reset_defaults()
126 smc->mib.fddiESSPayload = 0 ; in smt_reset_defaults()
127 smc->mib.fddiESSOverhead = 0 ; in smt_reset_defaults()
128 smc->mib.fddiESSMaxTNeg = (u_long)(- MS2BCLK(25)) ; in smt_reset_defaults()
129 smc->mib.fddiESSMinSegmentSize = 1 ; in smt_reset_defaults()
[all …]
H A Dpcmplc.c67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
75 #define PC1_BREAK 1
138 #define PS_BIT3 1
231 struct fddi_mib_p *mib ; in pcm_init() local
235 mib = phy->mib ; in pcm_init()
236 mib->fddiPORTPCMState = ACTIONS(PC0_OFF) ; in pcm_init()
241 mib->fddiPORTMy_Type = (np == PS) ? TS : TM ; in pcm_init()
244 mib->fddiPORTMy_Type = (np == PA) ? TA : in pcm_init()
248 mib->fddiPORTMy_Type = TM ; in pcm_init()
[all …]
H A Dsmt.c112 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0]) in is_my_addr()
114 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2]) in is_my_addr()
116 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[4])) ; in is_my_addr()
154 smc->mib.m[MAC0].fddiMACSMTAddress = smc->hw.fddi_home_addr ; in smt_agent_init()
159 smc->mib.fddiSMTStationId.sid_oem[0] = 0 ; in smt_agent_init()
160 smc->mib.fddiSMTStationId.sid_oem[1] = 0 ; in smt_agent_init()
161 driver_get_bia(smc,&smc->mib.fddiSMTStationId.sid_node) ; in smt_agent_init()
163 smc->mib.fddiSMTStationId.sid_node.a[i] = in smt_agent_init()
164 bitrev8(smc->mib.fddiSMTStationId.sid_node.a[i]); in smt_agent_init()
166 smc->mib.fddiSMTManufacturerData[0] = in smt_agent_init()
[all …]
H A Dcfm.c43 #define GO_STATE(x) (smc->mib.fddiSMTCF_State = (x)|AFLAG)
44 #define ACTIONS_DONE() (smc->mib.fddiSMTCF_State &= ~AFLAG)
76 #define CEM_PST_UP 1
97 smc->mib.fddiSMTCF_State = ACTIONS(SC0_ISOLATED) ; in cfm_init()
113 switch (phy->mib->fddiPORTMy_Type) { in selection_criteria()
222 smc->mib.fddiSMTCF_State & AFLAG ? "ACTIONS " : "", in cfm()
223 cfm_states[smc->mib.fddiSMTCF_State & ~AFLAG], in cfm()
225 state = smc->mib.fddiSMTCF_State ; in cfm()
228 } while (state != smc->mib.fddiSMTCF_State) ; in cfm()
235 if ( (smc->mib.fddiSMTCF_State == SC9_C_WRAP_A && in cfm()
[all …]
H A Drmt.c52 #define GO_STATE(x) (smc->mib.m[MAC0].fddiMACRMTState = (x)|AFLAG)
53 #define ACTIONS_DONE() (smc->mib.m[MAC0].fddiMACRMTState &= ~AFLAG)
57 #define RM1_NON_OP 1 /* not operational */
117 smc->mib.m[MAC0].fddiMACRMTState = ACTIONS(RM0_ISOLATED) ; in rmt_init()
120 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ; in rmt_init()
143 smc->mib.m[MAC0].fddiMACRMTState & AFLAG ? "ACTIONS " : "", in rmt()
144 rmt_states[smc->mib.m[MAC0].fddiMACRMTState & ~AFLAG], in rmt()
146 state = smc->mib.m[MAC0].fddiMACRMTState ; in rmt()
149 } while (state != smc->mib.m[MAC0].fddiMACRMTState) ; in rmt()
150 rmt_state_change(smc,(int)smc->mib.m[MAC0].fddiMACRMTState) ; in rmt()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c18 * name, device ID, page size, chip size in MiB, eraseblock size, options
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
68 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
69 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
70 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
71 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
72 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
74 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
75 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
[all …]
H A Dsm_common.c15 if (section > 1) in oob_sm_ooblayout_ecc()
19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()
33 case 1: in oob_sm_ooblayout_free()
82 case 1: in oob_sm_small_ooblayout_free()
106 memset(&oob, -1, SM_OOB_SIZE); in sm_block_markbad()
129 LEGACY_ID_NAND("SmartMedia 2MiB 3,3V ROM", 0x5d, 2, SZ_8K, NAND_ROM),
130 LEGACY_ID_NAND("SmartMedia 4MiB 3,3V", 0xe3, 4, SZ_8K, 0),
131 LEGACY_ID_NAND("SmartMedia 4MiB 3,3/5V", 0xe5, 4, SZ_8K, 0),
132 LEGACY_ID_NAND("SmartMedia 4MiB 5V", 0x6b, 4, SZ_8K, 0),
133 LEGACY_ID_NAND("SmartMedia 4MiB 3,3V ROM", 0xd5, 4, SZ_8K, NAND_ROM),
[all …]
/linux/include/net/
H A Dsnmp.h4 * SNMP MIB entries for the IP subsystem.
10 * however need to collect the MIB statistics and export them
127 #define __SNMP_INC_STATS(mib, field) \ argument
128 __this_cpu_inc(mib->mibs[field])
130 #define SNMP_INC_STATS_ATOMIC_LONG(mib, field) \ argument
131 atomic_long_inc(&mib->mibs[field])
133 #define SNMP_INC_STATS(mib, field) \ argument
134 this_cpu_inc(mib->mibs[field])
136 #define SNMP_DEC_STATS(mib, field) \ argument
137 this_cpu_dec(mib->mibs[field])
[all …]
/linux/Documentation/driver-api/cxl/
H A Dmemory-devices.rst33 given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
50 "host":"cxl_host_bridge.1",
54 "host":"cxl_switch_uport.1",
61 "pmem_size":"256.00 MiB (268.44 MB)",
62 "ram_size":"256.00 MiB (268.44 MB)",
64 "numa_node":1,
65 "host":"cxl_mem.1"
73 "pmem_size":"256.00 MiB (268.44 MB)",
74 "ram_size":"256.00 MiB (268.44 MB)",
76 "numa_node":1,
[all …]
/linux/Documentation/admin-guide/mm/damon/
H A Dstart.rst46 0 addr [85.541 TiB , 85.541 TiB ) (57.707 MiB ) access 0 % age 10.400 s
47 1 addr [85.541 TiB , 85.542 TiB ) (413.285 MiB) access 0 % age 11.400 s
48 2 addr [127.649 TiB , 127.649 TiB) (57.500 MiB ) access 0 % age 1.600 s
49 3 addr [127.649 TiB , 127.649 TiB) (32.500 MiB ) access 0 % age 500 ms
50 4 addr [127.649 TiB , 127.649 TiB) (9.535 MiB ) access 100 % age 300 ms
52 6 addr [127.649 TiB , 127.649 TiB) (6.926 MiB ) access 0 % age 1 s
56 total size: 577.590 MiB
68 (``age XX``). For example, the fifth region of ~9 MiB size is being most
87 access two 100 MiB sized memory regions one by one. You can substitute this
113 # access_frequency: 0 1 2 3 4 5 6 7 8 9
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Ddebugfs.c65 if (count && buf[count - 1] == '\n') in mt7915_sys_recovery_set()
66 buf[count - 1] = '\0'; in mt7915_sys_recovery_set()
76 * 1: trigger & enable system error L1 recovery. in mt7915_sys_recovery_set()
104 ret = mt7915_mcu_set_ser(dev, 1, 3, band); in mt7915_sys_recovery_set()
145 "1: trigger system error L1 recovery\n"); in mt7915_sys_recovery_get()
289 phy->mib.dl_cck_cnt, in mt7915_muru_stats_show()
290 phy->mib.dl_ofdm_cnt, in mt7915_muru_stats_show()
291 phy->mib.dl_htmix_cnt, in mt7915_muru_stats_show()
292 phy->mib.dl_htgf_cnt, in mt7915_muru_stats_show()
293 phy->mib.dl_vht_su_cnt); in mt7915_muru_stats_show()
[all …]
H A Dmain.c125 mt76_connac_mcu_set_pm(&dev->mt76, phy->mt76->band_idx, 1); in mt7915_stop()
130 mt76_connac_mcu_set_pm(&dev->mt76, dev->phy.mt76->band_idx, 1); in mt7915_stop()
150 /* prefer hw bssid slot 1-3 */ in get_omac_idx()
153 return i - 1; in get_omac_idx()
160 return i - 1; in get_omac_idx()
174 return i - 1; in get_omac_idx()
178 WARN_ON(1); in get_omac_idx()
182 return -1; in get_omac_idx()
256 mvif->sta.wcid.hw_key_idx = -1; in mt7915_add_interface()
274 memset(&mvif->cap, -1, sizeof(mvif->cap)); in mt7915_add_interface()
[all …]
H A Dmac.c17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Db44.h21 #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */
97 #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
152 #define MDIO_OP_WRITE 1
160 #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
184 #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */
186 #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */
187 #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */
188 #define B44_TX_O 0x0508UL /* MIB TX Octets */
189 #define B44_TX_P 0x050CUL /* MIB TX Packets */
190 #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */
[all …]
H A Dbcm63xx_enet.c98 return bcm_readl(bcm_enet_shared_base[1] + in enet_dmac_readl()
105 bcm_writel(val, bcm_enet_shared_base[1] + in enet_dmac_writel()
139 udelay(1); in do_mdio_op()
142 return (limit < 0) ? 1 : 0; in do_mdio_op()
159 return -1; in bcm_enet_mdio_read()
255 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { in bcm_enet_refill_rx()
268 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); in bcm_enet_refill_rx()
270 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan); in bcm_enet_refill_rx()
546 /* read mib registers in workqueue */ in bcm_enet_isr_mac()
680 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); in bcm_enet_set_mac_address()
[all …]
H A Dbcmsysport.c77 return BIT(bit + 1); in tdma_control_bit()
101 BCM_SYSPORT_INTR_L2(1)
227 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
228 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
229 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
230 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
231 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
232 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
233 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
234 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
[all …]
/linux/Documentation/translations/zh_TW/admin-guide/mm/damon/
H A Dstart.rst75 # access_frequency: 0 1 2 3 4 5 6 7 8 9
76 # x-axis: space (139728247021568-139728453431248: 196.848 MiB)
77 # y-axis: time (15256597248362-15326899978162: 1 m 10.303 s)
78 # resolution: 80x40 (2.461 MiB and 1.758 s for each character)
85 # avr: 107.708 MiB
87 10 95.328 MiB |**************************** |
88 20 95.332 MiB |**************************** |
89 30 95.340 MiB |**************************** |
90 40 95.387 MiB |**************************** |
91 50 95.387 MiB |**************************** |
[all …]
/linux/Documentation/translations/zh_CN/admin-guide/mm/damon/
H A Dstart.rst75 # access_frequency: 0 1 2 3 4 5 6 7 8 9
76 # x-axis: space (139728247021568-139728453431248: 196.848 MiB)
77 # y-axis: time (15256597248362-15326899978162: 1 m 10.303 s)
78 # resolution: 80x40 (2.461 MiB and 1.758 s for each character)
85 # avr: 107.708 MiB
87 10 95.328 MiB |**************************** |
88 20 95.332 MiB |**************************** |
89 30 95.340 MiB |**************************** |
90 40 95.387 MiB |**************************** |
91 50 95.387 MiB |**************************** |
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-caiman.dts23 wan_white@1 {
75 /* 128MiB */
78 #address-cells = <1>;
79 #size-cells = <1>;
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
[all …]
H A Darmada-385-linksys-cobra.dts23 wan_white@1 {
75 /* 128MiB */
78 #address-cells = <1>;
79 #size-cells = <1>;
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
[all …]
H A Darmada-385-linksys-shelby.dts23 wan_white@1 {
75 /* 128MiB */
78 #address-cells = <1>;
79 #size-cells = <1>;
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
[all …]
H A Darmada-385-linksys-rango.dts25 wan_white@1 {
83 /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */
86 #address-cells = <1>;
87 #size-cells = <1>;
91 reg = <0x0000000 0x200000>; /* 2MiB */
120 reg = <0xa00000 0x5000000>; /* 80MiB */
125 reg = <0x1000000 0x4a00000>; /* 74MiB */
131 reg = <0x5a00000 0x5000000>; /* 80MiB */
136 reg = <0x6000000 0x4a00000>; /* 74MiB */
140 * 86MiB, last MiB is for the BBT, not writable
[all …]
/linux/drivers/mtd/
H A Dssfdc.c27 the 128MiB) */
42 #define MiB(x) ( KiB(x) * 1024L ) macro
45 1MiB 2MiB 4MiB 8MiB 16MiB 32MiB 64MiB 128MiB
62 { MiB( 1), 125, 4, 4 },
63 { MiB( 2), 125, 4, 8 },
64 { MiB( 4), 250, 4, 8 },
65 { MiB( 8), 250, 4, 16 },
66 { MiB( 16), 500, 4, 16 },
67 { MiB( 32), 500, 8, 16 },
68 { MiB( 64), 500, 8, 32 },
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmain.c125 /* prefer hw bssid slot 1-3 */ in get_omac_idx()
128 return i - 1; in get_omac_idx()
135 return i - 1; in get_omac_idx()
149 return i - 1; in get_omac_idx()
153 WARN_ON(1); in get_omac_idx()
157 return -1; in get_omac_idx()
224 mvif->sta.wcid.hw_key_idx = -1; in mt7996_add_interface()
380 *wcid_keyidx = -1; in mt7996_set_key()
447 [IEEE80211_AC_BK] = 1, in mt7996_conf_tx()
577 mt76_wr(dev, MT_WF_PHYRX_BAND_GID_TAB_VLD1(band), mu[1]); in mt7996_update_mu_group()
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Drecommended.json104 "ScaleUnit": "1core clocks"
235 "PerPkg": "1",
236 "ScaleUnit": "6.103515625e-5MiB"
243 "PerPkg": "1",
244 "ScaleUnit": "6.103515625e-5MiB"
251 "PerPkg": "1",
252 "ScaleUnit": "6.103515625e-5MiB"
259 "PerPkg": "1",
260 "ScaleUnit": "6.103515625e-5MiB"
267 "PerPkg": "1",
[all …]

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