Lines Matching +full:1 +full:mib
77 return BIT(bit + 1); in tdma_control_bit()
101 BCM_SYSPORT_INTR_L2(1)
227 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
228 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
229 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
230 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
231 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
232 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
233 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
234 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
235 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
236 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
237 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
238 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
239 STAT_MIB_RX("rx_multicast", mib.rx.mca),
240 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
241 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
242 STAT_MIB_RX("rx_control", mib.rx.cf),
243 STAT_MIB_RX("rx_pause", mib.rx.pf),
244 STAT_MIB_RX("rx_unknown", mib.rx.uo),
245 STAT_MIB_RX("rx_align", mib.rx.aln),
246 STAT_MIB_RX("rx_outrange", mib.rx.flr),
247 STAT_MIB_RX("rx_code", mib.rx.cde),
248 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
249 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
250 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
251 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
252 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
253 STAT_MIB_RX("rx_unicast", mib.rx.uc),
254 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
255 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
257 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
258 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
259 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
260 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
261 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
262 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
263 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
264 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
265 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
266 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
267 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
268 STAT_MIB_TX("tx_multicast", mib.tx.mca),
269 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
270 STAT_MIB_TX("tx_pause", mib.tx.pf),
271 STAT_MIB_TX("tx_control", mib.tx.cf),
272 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
273 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
274 STAT_MIB_TX("tx_defer", mib.tx.drf),
275 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
276 STAT_MIB_TX("tx_single_col", mib.tx.scl),
277 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
278 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
279 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
280 STAT_MIB_TX("tx_frags", mib.tx.frg),
281 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
282 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
283 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
284 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
285 STAT_MIB_TX("tx_unicast", mib.tx.uc),
287 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
288 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
289 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
290 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
292 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
293 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
296 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
297 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
299 STAT_RDMA("rdma_ovflow_cnt", mib.rdma_ovflow_cnt, RDMA_OVFL_DISC_CNTR),
300 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
301 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
302 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
303 STAT_MIB_SOFT("tx_realloc_tsb", mib.tx_realloc_tsb),
304 STAT_MIB_SOFT("tx_realloc_tsb_failed", mib.tx_realloc_tsb_failed),
457 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); in bcm_sysport_update_mib_counters()
575 device_set_wakeup_enable(kdev, 1); in bcm_sysport_set_wol()
584 priv->wol_irq_disabled = 1; in bcm_sysport_set_wol()
657 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || in bcm_sysport_set_coalesce()
659 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) in bcm_sysport_set_coalesce()
707 priv->mib.alloc_rx_buff_failed++; in bcm_sysport_rx_refill()
715 priv->mib.rx_dma_failed++; in bcm_sysport_rx_refill()
944 if (likely(ring->clean_index < ring->size - 1)) in __bcm_sysport_tx_reclaim()
1262 priv->mib.tx_realloc_tsb_failed++; in bcm_sysport_insert_tsb()
1269 priv->mib.tx_realloc_tsb++; in bcm_sysport_insert_tsb()
1358 priv->mib.tx_dma_failed++; in bcm_sysport_xmit()
1425 changed = 1; in bcm_sysport_adj_link()
1430 changed = 1; in bcm_sysport_adj_link()
1459 changed = 1; in bcm_sysport_adj_link()
1543 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); in bcm_sysport_init_tx_ring()
1586 1 << RING_HYST_THRESH_SHIFT, in bcm_sysport_init_tx_ring()
1591 reg |= (1 << index); in bcm_sysport_init_tx_ring()
1735 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO); in bcm_sysport_init_rx_ring()
1812 * to be processed (1 msec). in umac_enable_set()
1837 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | in umac_set_hw_addr()
1854 mdelay(1); in topctrl_flush()
2010 priv->old_duplex = -1; in bcm_sysport_open()
2011 priv->old_link = -1; in bcm_sysport_open()
2012 priv->old_pause = -1; in bcm_sysport_open()
2054 ret = rdma_enable_set(priv, 1); in bcm_sysport_open()
2059 ret = tdma_enable_set(priv, 1); in bcm_sysport_open()
2064 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); in bcm_sysport_open()
2350 * 1:1 mapping, we can only do a 2:1 mapping. By reducing the number of in bcm_sysport_map_queues()
2501 rxq = 1; in bcm_sysport_probe()
2534 priv->irq1 = platform_get_irq(pdev, 1); in bcm_sysport_probe()
2537 priv->wol_irq = platform_get_irq_optional(pdev, 1); in bcm_sysport_probe()
2592 priv->wol_irq_disabled = 1; in bcm_sysport_probe()
2596 device_set_wakeup_capable(&pdev->dev, 1); in bcm_sysport_probe()
2611 priv->rx_max_coalesced_frames = 1; in bcm_sysport_probe()
2728 umac_enable_set(priv, CMD_RX_EN, 1); in bcm_sysport_suspend_to_wol()
2848 ret = rdma_enable_set(priv, 1); in bcm_sysport_resume()
2868 umac_enable_set(priv, CMD_RX_EN, 1); in bcm_sysport_resume()
2873 umac_enable_set(priv, CMD_TX_EN, 1); in bcm_sysport_resume()
2875 ret = tdma_enable_set(priv, 1); in bcm_sysport_resume()