Lines Matching +full:1 +full:mib
21 #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */
97 #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
152 #define MDIO_OP_WRITE 1
160 #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
184 #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */
186 #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */
187 #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */
188 #define B44_TX_O 0x0508UL /* MIB TX Octets */
189 #define B44_TX_P 0x050CUL /* MIB TX Packets */
190 #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */
191 #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */
192 #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */
193 #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */
194 #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */
195 #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */
196 #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */
197 #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */
198 #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */
199 #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */
200 #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */
201 #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */
202 #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */
203 #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */
204 #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */
205 #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */
206 #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */
207 #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */
208 #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */
209 #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */
210 #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */
211 #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */
212 #define B44_RX_O 0x0588UL /* MIB RX Octets */
213 #define B44_RX_P 0x058CUL /* MIB RX Packets */
214 #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */
215 #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */
216 #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */
217 #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */
218 #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */
219 #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */
220 #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */
221 #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */
222 #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */
223 #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */
224 #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */
225 #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */
226 #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */
227 #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */
228 #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */
229 #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */
230 #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */
231 #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
232 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
237 #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */